FPGA Front Runner: FPGA Safety and Security
FPGA Front Runner: FPGA Safety and Security
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FPGA Safety and Security
This event covers the challenges in ensuring an FPGA is secure and demonstrably safe as per the relevant industry safety standards. This includes supply chains, FPGA hardware and the IP used on the FPGA
Agenda (GMT)
Time |
Speaker |
Details |
09.30 |
Arrival and registration |
|
10.00 |
Tobias Adryan, Synopsys |
Securing FPGAs Beyond the Bitstream |
10.30 |
Espen Tallaksen, EmLogic |
FPGA Requirements Tracking and the Requirements Traceability Matrix |
11.00 |
Andrew Swirski, Beetlebox |
Securing FPGA Development Pipelines with DevSecOps |
11.30 |
Refreshment break |
|
12.00 |
Ian Pearson, Microchip Technology Inc. |
EU Cyber Resilience Act – Impacts on Business and Product Design |
12.30 |
Flemming Christensen, Sundance Multiprocessor Technology Ltd |
How to secure supply of ‘COTS’ FPGA Modules |
13.00 |
Peter Davies, Thales |
|
13.30 |
Lunch and networking |
|
14.00 |
End |
|
FPGA Front Runner event Partner: TechWorks & Tessolve
NOTE
Please be aware that if you register for both the in-person and virtual events, your physical ticket will be cancelled, preventing access on the event day.
We also maintain a blacklist; individuals who register for the in-person event but fail to attend will be restricted from participating in future events. If you book a physical ticket but cannot attend then please cancel it in advance.
Location
The Cass Centre, Shaftesbury Road, Cambridge, CB2 8BS