FPGA Front Runner - Using AI in development and product for FPGA
FPGA Front Runner - Using AI in development and product for FPGA
FPGA Front Runner - Using AI in development and product for FPGA
How are they used? What input language is used and how does it find it’s way into the FPGA?
How is the AI trained?
Any use case example
Agenda (GMT)
Time |
Speaker |
Details |
09.00 |
Arrival and registration |
|
09:30 |
Pete Leonard, Renishaw, Electronics Design Manager – Group Engineering |
Introduction to Renishaw |
09:40 |
Gareth Richards, TechWorks AI Network Manager |
An Introduction to Techworks-AI |
10:00 |
Petros Toupas, Heronic Technologies, CTO |
Automating the design of bespoke AI accelerator IP |
10:30 |
James Lewis , RED Semiconductor CEO |
VISC – A microprocessor accelerator architecture in FPGA |
11:00 |
Dr Pedro Machado, Nottingham Trent University, Senior Lecturer in Computer Science |
Novel bio-inspired encryption using SNNs suitable for FPGA: A Privacy-Preserving Approach |
11:30 |
Refreshment break |
|
12:00 |
Jeremy Bennett (speaker) & William Jones, Embecosm, Chief Executive (Bennett), Head of AI/ML (Jones) |
How to port AI systems to new computer architectures |
12:30 |
Giles Peckham, Myrtle.ai, Head Of Marketing |
Realising the enormous potential of FPGAs for machine learning |
13:00 |
Mark Azadpour, AWS, Sr. HPC GTM |
AI in development and proto-typing for FPGA |
13:30 |
Lunch |
|
14:00 |
End |
|
Sponsors
FPGA Front Runner event is made possible through the generous support of our sponsors: Renishaw Partner: TechWorks & Tessolve
NOTE
Please be aware that if you register for both the in-person and virtual events, your physical ticket will be cancelled, preventing access on the event day.
We also maintain a blacklist; individuals who register for the in-person event but fail to attend will be restricted from participating in future events. If you book a physical ticket but cannot attend then please cancel it in advance.
Location
Renishaw plc, New Mills, Wotton-under-Edge , Gloucestershire, GL12 8JR