[3 sessions] Simulation-Based Verification Training Series

Consists of the three sessions:

• 15th Jan 2025 - SystemVerilog – Foundations for Verification
• 22nd Jan 2025 - Verification Using SystemVerilog – Practical Approaches & Techniques
• 29th Jan 2025 - Introduction to UVM – Universal Verification Methodology

This comprehensive three-part training series is designed to build a solid foundation in simulation-based verification using SystemVerilog and UVM. Across three focused sessions, you'll learn the essential concepts, methodologies, and practical techniques needed to write efficient, scalable, and effective verification environments. Whether you're new to verification or looking to strengthen your skills, this bundle provides a cohesive, structured path toward mastering modern simulation-based verification.