RISC-V Verification

This session will be recorded and will be available to all registrants post-session.

RISC-V is rapidly transforming the semiconductor landscape with its open and extensible instruction set architecture. As adoption accelerates across industries, the need for robust and scalable verification methodologies has never been more critical.

Join us at DV Club Cambridge as we dive into the latest innovations and challenges in RISC-V verification. This event will bring together leading experts to share real-world insights, best practices, and advanced techniques for verifying RISC-V cores and complex systems. Whether you're building commercial RISC-V products or exploring open-source initiatives, this is a must-attend for anyone passionate about quality and reliability in hardware design.

Agenda (GMT)

         Time                    Details

         12.00                   Arrival, registration, networking, light refreshments

         13:00                   Max RISCV-DV
                                      by Puneet Goel, Coverify Systems Technology LLP

         13:20                   Applying System Verification Techniques to RISC-V Core and Subsystem Validation
                                      by David Kelf, Breker Verification Systems

         13:50                   Reliable Hardware Trojan Detection for RISC-V Processors using Formal Verification
                                      by Christian Appold, DENSO AUTOMOTIVE Deutschland GmbH

         14:10                   RISC-V software and logic co-development with OSVVM co-simulation
                                      by Simon Southwell, Wyvern Semiconductors

         14.30                   Foundational verification of logical equivalence checking
                                      by Michalis Pardalos, Imperial College London

         14.50                  RISC-V Verification with Jasper
                                     by Nupur Verma, Cadence

         15:15                   Break with refreshments/networking

         15:45                   Ibex: going from university core to commercial tape-out
                                      by Dr Marno van der Maas, lowRISC

         16:10                   From the Sail-RISC-V spec to a Verilog model for verification
                                      by Dr Alasdair Armstrong, University of Cambridge

         16:40                   Formal Verification of CHERI RISC-V Processors
                                      by Prof Tom Melham, University of Oxford

         17:10                   Refreshments/networking   

VENUE:
How to get to the venue: https://www.cst.cam.ac.uk/directions
Parking: Madingley Road Park and Ride (10 minutes walk away from the venue)

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