Security Verification

This session will be recorded and will be available to all registrants post-session.

As systems grow more complex and interconnected, security has become a critical verification challenge rather than an afterthought. Verifying security requirements alongside functional correctness is now essential for building robust, trustworthy designs.

This DV Club Zurich session focuses on security verification, exploring practical approaches to verifying security properties in modern systems. Topics include security verification challenges in IPs, complex SoCs and system-scale designs, the impact of threat modelling on verification strategies, and lessons learned from real-world projects.

The discussion will emphasise what works in practice, sharing experiences, techniques, and insights from researchers, engineers and verification professionals dealing with security-critical designs today.

Agenda (CEST)

         Time                    Details

         12.00                   Arrival, registration, networking, light refreshments         

         13:00                  Welcome remarks

         13:05                   Leveraging Invariants for Scalable Verification of
                                      RISC-V Cryptography Extensions
                                      by Kim Fahrni, Katharina Ceesay-Seitz, Denis Zuppiger and Kaveh Razavi
                                      ETH Zurich

         13:25                   HartBreaker: Deterministic Fuzzing of Multi-Hart RISC-V CPUs
                                      with Non-Deterministic Programs
                                      by Quentin Bordier, ETH Zurich

         13:45                   TRISTAN: Custom RISC-V Instruction Set Extensions
                                       by Patrick Sieberer, Semify EDA

         14:15                   A Layered Multidisciplinary Approach to RISC-V Basic Software
                                      by Emilio Guijarro, Quintauris

         14:40                   Confidentiality Assurance using Sentry:
                                      A Key Component Of Hardware Security
                                      by Vikas Sachdeva, Real Intent

         15:05                  Break with refreshments/networking

         16:05                  SoC Security
                                     by Mike Bartley, Alpinum Consulting

         16:20                  Automated Detection of Hardware Vulnerabilities with ALVIE
                                      by Matteo Busi, Ca’ Foscari University of Venice

         16:45                  RISC-V software and logic co-development with OSVVM co-simulation
                                      by Simon Southwell, Wyvern Semiconductors

         17:10                   Formal Verification of CHERI-CVA6: End-to-End and Beyond
                                      by Louis-Emile Ploix, lowRISC CIC

         17:35                   Crucible: Retrofitting Commodity CPUs with Vulnerabilities
                                      via Transparent Software Emulation
                                      by Tristan Hornetz, CISPA Helmholtz Center for Information Security

          18:00                  Refreshments/networking   

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