AMS Co-Simulation Training in Reading, UK or online

AMS Co-Simulation Training in Reading, UK or online

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Format: Hybrid: In-person and online
Breakfast, lunch and snacks included.

Overview

Learn how to build and verify power-aware mixed-signal systems using UPF, SystemVerilog, SPICE, and UVM methodologies.

This intensive 1-day training provides a practical introduction to AMS co-simulation workflows used in modern low-power semiconductor verification environments. Participants will explore how analog and digital domains interact across voltage boundaries while applying industry-standard methodologies for power-aware verification and debugging.

The training combines theory, practical examples, and real-world debugging techniques used in mixed-signal verification projects.

Topics include:

• AMS and UPF integration

• Power-aware mixed-signal verification

• Boundary management across voltage domains

• UVM power sequencing methodologies

• Debugging convergence and X-corruption issues

Designed for engineers working on low-power semiconductor and mixed-signal verification environments.

Learning Objectives

By the end of this session, participants will be able to:

• Understand AMS + UPF verification methodologies

• Configure power-aware mixed-signal verification environments

• Apply isolation and level-shifting strategies across voltage domains

• Integrate UVM methodologies into AMS verification workflows

• Debug shutdown, ramp-up, convergence, and X-corruption issues effectively

• Build scalable AMS co-simulation verification flows

Agenda

AMS & UPF Fundamentals

• SystemVerilog & Verilog-AMS syntax refresher

• UPF 1801 fundamentals

• Power domains and Power State Tables (PSTs)

• SPICE modeling basics

• VCS and PrimeSim synchronization

Power-Aware Boundary Management

• Connect module configuration

• L2E / E2L conversion strategies

• Isolation cell methodologies

• Level shifter integration

• Multi-voltage domain management

• VCS-NLP compilation flow

PA-UVM & Debug Methodologies

• UVM power sequencing

• Power-aware waveform and FSDB generation

• Verdi PA & AMS debugging

• X-corruption analysis

• Convergence debugging methodologies

Capstone Exercise

• Power-Aware SAR ADC Verification Lab

Who Should Attend?

• Design Verification Engineers

• AMS / Mixed-Signal Engineers

• Low-Power Verification Engineers

• UVM Verification Engineers

• Verification Leads & Architects

Training Format

• Live online instructor-led training

• Interactive Q&A throughout

• Practical industry-focused examples

• Recording access included for attendees

Key Benefits

✔ Learn practical UPF + AMS integration methodologies
✔ Improve low-power mixed-signal verification workflows
✔ Debug power-aware AMS systems more effectively
✔ Build scalable PA-UVM verification environments
✔ Apply concepts directly to real semiconductor projects

Register today – places are limited to 20 participants.