RISC-V Verification Training in San Jose, CA or online

RISC-V Verification Training in San Jose, CA or online

We offer 50% discount to students, please complete this form to avail discount.

First 10 registrants for only $300

Breakfast, lunch and snacks included.

Overview

Master RISC-V CPU and SoC verification in this practical, expert-led training. Learn how to plan, implement, and validate CPU and SoC designs using modern verification strategies and open-source tools.

Who Should Attend

• Engineers working on CPU/SoC projects or interested in RISC-V verification.

• Participants with basic digital design and programming experience (Verilog/SystemVerilog, C, or assembler).

Learning Objectives

Participants will gain the skills to:

• Understand CPU architectures and microarchitectures.

• Develop verification strategies for CPUs and SoCs.

• Use RISC-V instruction streams, riscv-dv tools, and simulators effectively.

• Apply practical SoC verification techniques, including feature verification, debug, and functional coverage.

Agenda Highlights

• CPU verification at unit, CPU, and system levels

• Instruction stream generation and riscv-dv tooling

• RISC-V ISA, assembler, and C programming

• CPU integration in SoC verification

• SoC debug, functional coverage, and sign-off procedures

• Practical exercises and classroom review

Register now – only 20 participants will be accommodated.