Hands-on Training: AI in Design Verification in San Jose, CA or online

Hands-on Training: AI in Design Verification in San Jose, CA or online

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

First 10 registrants for only $300

Format: Hybrid: In-person and online
Breakfast, lunch and snacks included.

Overview

Step into the future of verification with this AI in Design Verification Hands-on Training — a highly interactive, full-day experience where engineers build, test, and experiment with AI-driven DV workflows in real time.

Rather than traditional training, participants will apply Generative AI, Machine Learning, and Reinforcement Learning techniques to solve practical verification challenges — from automated UVM generation to intelligent debug and coverage optimization.

Guided by expert mentors, this Hands-on Training is designed to help you move from theory to real implementation in a single day.

Hands-on Training Challenge

Participants will work individually or in small teams on a real-world DV problem set, with challenges such as:

• Generating UVM components from specifications using LLMs

• Automating testbench creation with AI assistance

• Applying ML techniques to log analysis and coverage prediction

• Using RL / Genetic Algorithms for intelligent test generation

• Improving coverage closure using AI-driven insights

• Debugging failing designs with AI-assisted workflows

What you'll gain

By the end of the Hands-on Training , participants will:

• Understand how AI (GenAI, ML, RL, GA) applies to real DV workflows

• Build AI-assisted verification flows using modern tools

• Accelerate testbench creation and debug cycles

• Explore practical AI integration into SystemVerilog / UVM environments

• Evaluate AI tools for enterprise deployment

• Identify immediate, high-impact use cases for their teams

Format

• Kick-off session: AI fundamentals + challenge briefing

• Hands-on hacking: Solve real DV problems using AI tools

• Mentor support: Continuous guidance from DV & AI experts

• Live experimentation: Try different models, prompts, and workflows

• Final demos: Showcase solutions and approaches

• Wrap-up: Key learnings, best practices, and next steps

Who Should Join

• Design Verification engineers (SystemVerilog / UVM)

• RTL and SoC engineers exploring AI-driven workflows

• Technical leads evaluating AI adoption in DV

• Engineers looking to boost productivity and reduce manual effort

Key Themes Covered

• AI Foundations: GenAI, ML, RL, Genetic Algorithms

• AI in RTL: Auto-coding, linting, PPA optimisation

• AI in Verification:

  • Spec-to-UVM generation

  • AI-driven testbench architecture

  • ML for log analysis & coverage prediction

  • RL/GA for intelligent stimulus generation

• Tools & Integration:

  • Open-source vs enterprise AI stacks

  • Integration with Synopsys VCS & Cadence Xcelium

  • Security, guardrails, and handling proprietary RTL

• Future of DV: Autonomous verification workflows

Limited to 12 participants to ensure a highly interactive, high-impact experience with direct expert support.