[3 sessions] AMS Co-Simulation (RNM & UVM)

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the three sessions:

• 4 August 2026 – AMS Co-Simulation Fundamentals
• 11 August 2026 – Compilation, Power & RNM
• 18 August 2026 – UVM Integration & Debug

Learn how modern mixed-signal verification environments integrate SystemVerilog, Verilog-AMS, SPICE, RNM, and UVM methodologies.

This live online training series covers:

• AMS co-simulation fundamentals

• Real Number Modeling (RNM)

• UVM integration for mixed-signal verification

• Power-aware verification concepts

• Debugging and optimization techniques

Designed for engineers working across digital, analog, and mixed-signal verification domains.

What You Will Learn

By the end of this series, you will:

• Understand AMS co-simulation architectures

• Use Verilog-A and SPICE in mixed-signal environments

• Apply RNM for faster verification

• Integrate UVM with analog/mixed-signal systems

• Debug AMS simulations using industry workflows

Who Should Attend

• Design Verification Engineers

• AMS / Mixed-Signal Engineers

• UVM Verification Engineers

• RTL Engineers moving into AMS

• Verification Leads & Architects