[3 sessions] AMS Co-Simulation (Power-Aware / UPF)

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the three sessions:

• 13 August 2026 – AMS & UPF Fundamentals
• 20 August 2026 – Power-Aware Boundary Management
• 27 August 2026 – PA-UVM & Debug

Learn how to build and verify power-aware mixed-signal systems using UPF, SystemVerilog, SPICE, and UVM methodologies.

This live online training series focuses on:

• AMS and UPF integration

• Power-aware mixed-signal verification

• Boundary management across voltage domains

• UVM power sequencing

• Debugging convergence and X-corruption issues

Designed for engineers working on low-power semiconductor and mixed-signal verification environments.

What You Will Learn

By the end of this series, you will:

• Understand AMS + UPF verification flows

• Configure power-aware mixed-signal environments

• Apply isolation and level shifting strategies

• Integrate UVM with power-aware AMS verification

• Debug shutdown, ramp-up, and convergence issues

Who Should Attend

• Design Verification Engineers

• AMS / Mixed-Signal Engineers

• Low-Power Verification Engineers

• UVM Verification Engineers

• Verification Leads & Architects

Course Structure

Session 1: AMS & UPF Fundamentals

• Verilog-AMS and SystemVerilog basics

• UPF 1801 fundamentals

• Power domains and Power State Tables

• SPICE modeling basics

• VCS and PrimeSim synchronization

Session 2: Power-Aware Boundary Management

• Connect modules and threshold mapping

• Isolation cell strategies

• Level shifter integration

• Multi-voltage domain management

• VCS-NLP compilation flow

Session 3: PA-UVM & Debug

• UVM power sequencing

• Power-aware waveform generation

• Verdi PA & AMS debugging

• X-corruption and convergence analysis

• Mixed-signal debug methodologies

Capstone Exercise

Power-Aware SAR ADC Verification Lab

Training Format

• Live online interactive sessions

• 3 × 2-hour sessions

• Includes Q&A and practical examples

Key Benefits

✔ Learn practical UPF + AMS integration
✔ Improve low-power verification workflows
✔ Debug power-aware mixed-signal systems effectively
✔ Build scalable PA-UVM verification environments