[3 Parts ] Low-Power Verification

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the three sessions:

23-24 September 2026 – Low-Power Foundations & Power-Aware RTL Verification

28-29 September 2026 – CPU, Firmware & Low-Power Software Verification

30 September, 1 October 2026 – SoC Power Management, Formal Verification & Verification Sign-Off

Course Overview

Master the methodologies for verifying modern low-power semiconductor designs, from block-level power intent verification to full System-on-Chip (SoC) power management and verification sign-off.

This comprehensive live online training series provides engineers with a practical understanding of low-power verification using industry-standard methodologies, including Unified Power Format (UPF), power-aware simulation, SystemVerilog Assertions (SVA), UVM, Dynamic Voltage and Frequency Scaling (DVFS), firmware co-verification, and SoC power management.

Throughout the programme, participants will explore how modern semiconductor devices implement and verify advanced power-saving techniques while maintaining functional correctness, performance, and reliability. Using real-world examples, practical demonstrations, and structured verification workflows, the course develops the skills needed to verify increasingly complex low-power digital systems.

What You Will Learn

By the end of this training series, you will:

• Understand the complete low-power verification lifecycle from RTL to full SoC integration

• Learn how power intent is specified, implemented, and verified using UPF

• Apply power-aware verification methodologies using UVM, SVA, and simulation-based workflows

• Verify isolation, retention, level shifters, and power domain interactions

• Explore DVFS and CPU power management verification techniques

• Understand firmware-controlled power management and software interaction

• Learn how Power Management Units (PMUs) coordinate power states across modern SoCs

• Verify suspend, resume, and wake-up sequences across multiple power domains

• Apply formal verification techniques to validate low-power architectures

• Develop verification plans and sign-off strategies for production-ready low-power designs

Course Structure

Part 1 — Low-Power Foundations & Power-Aware RTL Verification

Sessions 1–2

Build a strong understanding of low-power design principles by learning how power intent is defined, implemented, and verified at the RTL level using industry-standard methodologies.

Topics include:

• Low-power design fundamentals

• Unified Power Format (UPF)

• Power domains and power intent

• Clock gating methodologies

• Power gating verification

• Isolation cell verification

• Retention register verification

• Level shifter verification

• Power-aware simulation

• UVM methodologies for low-power verification

• SystemVerilog Assertions for power-aware verification

• Debugging power intent implementation

Part 2 — CPU, Firmware & Low-Power Software Verification

Sessions 3–4

Explore how processors, firmware, and operating software manage power across modern semiconductor devices while ensuring correct functionality and performance.

Topics include:

• Dynamic Voltage and Frequency Scaling (DVFS)

• CPU power state verification

• Firmware-controlled power management

• Power Management Unit (PMU) architecture

• Suspend and resume verification

• Wake-up sequence validation

• CPU idle states

• Peripheral power management

• Interrupt handling during power transitions

• Linux power management fundamentals

• Hardware/software co-verification

• Firmware debugging for low-power systems

Part 3 — SoC Power Management, Formal Verification & Verification Sign-Off

Sessions 5–6

Learn how low-power verification scales to complete SoCs through advanced power management strategies, formal verification, coverage analysis, and verification sign-off methodologies.

Topics include:

• SoC power architecture

• Multi-domain power verification

• Cross-domain power interactions

• Power-aware formal verification

• Functional and power coverage analysis

• Verification planning and closure

• Power management verification strategies

• Sign-off requirements

• Silicon correlation and validation

• Debugging complex power scenarios

• Best practices for verification closure

• End-to-end low-power verification workflows

Who Should Attend

This course is ideal for:

• Design Verification Engineers

• RTL Design Engineers

• ASIC & SoC Engineers

• FPGA Engineers

• Embedded Software Engineers

• Firmware Engineers

• Low-Power Verification Engineers

• Power Architecture Engineers

• UVM Verification Engineers

• Technical Leads responsible for low-power design and verification

Training Format

• Live online instructor-led training

• Three progressive learning modules

• Two consecutive training sessions per part

• Four hours of live instruction per session

• Interactive demonstrations and practical walkthroughs

• Real-world semiconductor case studies

• Hands-on verification methodologies and debugging techniques

• Interactive Q&A sessions and technical discussions

What's Included

• Live instructor-led training

• Comprehensive digital course materials

• Practical demonstrations and real-world examples

• Interactive Q&A sessions with experienced instructors

• Certificate of Completion

Key Benefits

✔ Develop practical expertise in modern low-power verification methodologies

✔ Learn how to verify UPF implementations across RTL, CPU, and SoC levels

✔ Gain confidence using power-aware UVM, SVA, and simulation workflows

✔ Understand firmware, PMU, and operating system interaction with hardware power management

✔ Build practical skills in DVFS, power gating, isolation, and retention verification

✔ Learn formal verification and coverage methodologies for low-power designs

✔ Improve verification efficiency using structured planning and sign-off workflows

✔ Strengthen your expertise in developing reliable, energy-efficient semiconductor systems