[ 3 Parts ] Multi-Level Hardware Debug

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the three sessions:

• 12-13 October 2026 –  Block-Level RTL Debug
• 14-15 October 2026 – CPU HW/SW Debug
• 19-20 October 2026 – SoC HW & HW/SW Debug
  
  Course Overview
  
  Master modern hardware debugging techniques across the complete semiconductor development lifecycle—from RTL block-level verification through CPU hardware/software debugging to full SoC bring-up and post-silicon validation.
  
  This comprehensive live online training series provides a structured, practical approach to debugging increasingly complex digital systems using industry-standard methodologies, commercial EDA tools, open-source frameworks, and real-world case studies.
  
  Throughout the programme, participants will learn how experienced verification and bring-up engineers identify, isolate, analyse, and resolve design issues across RTL simulation, CPU debug environments, and complete System-on-Chip platforms.
  
  The programme focuses on:
  
  
  • RTL simulation and waveform-based debugging methodologies
    
  • Structured debug workflows using the DARE methodology
    
  • UVM log analysis and assertion-based verification
    
  • Coverage-driven and formal verification debug techniques
    
  • CPU hardware/software debugging using GDB and OpenOCD
    
  • RISC-V Debug Module architecture and trigger mechanisms
    
  • Multi-core software and hardware debugging strategies
    
  • SoC bring-up, trace analysis and post-silicon validation
    
  • Hardware/software integration and full-stack debug workflows
    
  • Industry best practices for efficient debug and verification closure
    
    
  Designed for verification engineers, RTL designers, CPU architects, embedded software engineers, SoC developers, and hardware bring-up teams looking to strengthen practical debugging skills across modern semiconductor development.

What You Will Learn

By the end of this training series, you will:

• Build a structured methodology for analysing and resolving hardware design issues

• Learn professional RTL debugging techniques using simulation, assertions, and waveform analysis

• Apply coverage-driven and formal verification to isolate complex design failures

• Understand CPU debugging using GDB, OpenOCD, JTAG and the RISC-V Debug Module

• Debug software running on both simulated and physical hardware targets

• Diagnose multi-core synchronisation, race conditions and deadlocks

• Explore SoC-level bring-up, trace infrastructure and post-silicon validation

• Bridge hardware and software debugging into a single end-to-end workflow

• Gain practical experience through demonstrations, case studies and real debugging scenarios

• Develop debugging techniques used by professional verification and silicon validation team

Who Should Attend

This course is ideal for:

• RTL Design Engineers

• Verification Engineers

• ASIC & SoC Design Engineers

• CPU & Processor Verification Engineers

• FPGA Engineers

• Embedded Software Engineers

• Hardware Bring-Up Engineers

• Silicon Validation Engineers

• UVM Verification Engineers

• Formal Verification Engineers

• Technical Leads and Engineering Managers involved in digital design verification.

Course Structure

Part 1 — Block-Level RTL Debug

Sessions 1–2

Develop a strong foundation in RTL debugging by learning structured debug methodologies, simulation workflows, waveform analysis, assertion-based verification, coverage-driven debugging and formal verification techniques.

Topics include:

• Verification flow and RTL bug classification

• The DARE Debug methodology

• UVM log analysis

• Waveform debugging techniques

• X-propagation analysis

• SystemVerilog Assertions

• Deadlock and livelock diagnosis

• Coverage-driven debugging

• Counterexample (CEX) analysis

• Formal verification workflows

• Regression triage

• Professional EDA debug workflows

Part 2 — CPU HW/SW Debug

(Single-Core, Multi-Core & Application-Level)

Sessions 3–4

Explore how modern processors are debugged using both software and hardware tools, learning practical workflows from JTAG interfaces through to multi-core application debugging.

Topics include:

• Hardware and software debug fundamentals

• OpenOCD and GDB integration

• Breakpoints and watchpoints

• RISC-V Debug Module architecture

• Program Buffer and System Bus Access

• Trigger modules and hardware debugging

• Single-core debugging workflows

• Multi-core synchronisation

• Race condition analysis

• RTOS-aware debugging

• Linux application debugging

• Production firmware debugging techniques

Part 3 — SoC HW & HW/SW Debug

Sessions 5–6

Learn how debugging scales to complete System-on-Chip platforms, covering hardware bring-up, trace infrastructure, software integration and full end-to-end debug strategies.

Topics include:

• SoC debug architecture

• JTAG and Debug Access Ports

• Hardware bring-up methodologies

• Trace infrastructure

• Post-silicon validation

• Hardware/software integration

• Memory map debugging

• Peripheral debugging

• Interrupt and exception analysis

• Multi-core SoC debugging

• Bare-metal, RTOS and Linux debugging

• Complete end-to-end debug workflows

Training Format

• Live online instructor-led training

• Three progressive learning modules

• Two consecutive training sessions per part

• Four hours of live instruction per session

• Interactive demonstrations and technical walkthroughs

• Real debugging scenarios and industry case studies

• Practical workflows using commercial and open-source debugging tools

• Q&A sessions and technical discussions throughout the course

Key Benefits

✔ Develop a structured methodology for debugging complex digital hardware

✔ Learn practical RTL, CPU and SoC debugging workflows used in industry

✔ Build confidence using professional debug tools including GDB, OpenOCD and modern EDA environments

✔ Understand how hardware and software debugging integrate across modern semiconductor platforms

✔ Gain practical insight into simulation, formal verification, waveform analysis and silicon bring-up

✔ Improve debugging efficiency through proven methodologies and real-world engineering examples

✔ Learn techniques applicable to ASIC, FPGA, CPU and SoC development projects

✔ Build end-to-end debugging skills from RTL verification to production silicon