Low-Power Verification Training

Part 1 – Low-Power Foundations & Power-Aware RTL Verification

2-Session Intensive Live Online Training

Build a strong foundation in modern low-power verification by learning how power intent is created, implemented, and verified at the RTL level using industry-standard methodologies.

This hands-on, live online course introduces the essential verification techniques for developing reliable and energy-efficient semiconductor designs. Participants will learn how modern digital systems implement low-power architectures using Unified Power Format (UPF), power-aware simulation, SystemVerilog Assertions (SVA), and UVM verification methodologies.

Format

Delivery: Live Online

Duration: 2 Consecutive sessions

Daily Schedule: 4 Hours per session

Total Training: 8 Hours

Price: $60

Register for Part 1

Whether you are beginning your low-power verification journey or strengthening your RTL verification expertise, this course provides the practical knowledge required to verify power-aware digital designs before full SoC integration.

Course Overview

Modern semiconductor devices rely heavily on sophisticated low-power techniques to reduce energy consumption while maintaining functionality and performance. Correct implementation of these techniques begins during RTL development, making early verification essential.

During this two-session course, participants will learn how power intent is specified using Unified Power Format (UPF), how multiple power domains interact, and how verification engineers validate power-aware behavior through simulation and assertion-based verification.

Real-world examples and practical verification workflows demonstrate how engineers verify isolation cells, retention registers, level shifters, clock gating, and power gating throughout the RTL development process.

What You Will Learn

By the end of this course, you will be able to:

• Understand modern low-power design principles

• Define and verify power intent using Unified Power Format (UPF)

• Implement power-aware RTL verification methodologies

• Verify power domains and domain interactions

• Validate clock gating implementation

• Verify power gating functionality

• Verify isolation cells

• Verify retention registers

• Validate level shifters

• Perform power-aware simulation

• Apply UVM methodologies for low-power verification

• Develop SystemVerilog Assertions (SVA) for power-aware verification

• Debug common power intent implementation issues

Course Topics

Low-Power Design Fundamentals

• Why low-power design matters

• Sources of power consumption

• Static vs dynamic power

• Low-power architecture overview

Unified Power Format (UPF)

• Introduction to UPF

• Creating power intent

• UPF syntax and structure

• Applying UPF within RTL designs

Power Domains & Power Intent

• Power domain creation

• Supply networks

• Domain interaction

• Power state management

Clock Gating Methodologies

• Clock gating architectures

• Verification strategies

• Common implementation challenges

Power Gating Verification

• Switch control verification

• Power sequencing

• Functional correctness during shutdown

Isolation Cell Verification

• Isolation strategies

• Control signal verification

• Power-off behavior

Retention Register Verification

• State preservation

• Save and restore sequences

• Retention validation

Level Shifter Verification

• Voltage domain crossing

• Signal integrity

• Verification methodologies

Power-Aware Verification

• Power-aware simulation

• UVM integration

• Assertion-based verification

• Debugging power intent

Who Should Attend

This course is ideal for:

• Design Verification Engineers

• RTL Design Engineers

• ASIC Engineers

• FPGA Engineers

• Low-Power Verification Engineers

• UVM Engineers

• Semiconductor Engineers

• Hardware Verification Engineers

• Technical Leads

Training Format

• Live instructor-led online sessions

• Interactive demonstrations

• Practical verification workflows

• Real-world semiconductor examples

• Q&A with experienced instructors

What's Included

• Live instructor-led training

• Digital course materials

• Practical demonstrations

• Interactive Q&A sessions

• Certificate of Completion

Key Benefits

✔ Build a strong foundation in low-power verification

✔ Learn UPF implementation and verification

✔ Understand power-aware simulation techniques

✔ Apply UVM and SVA to low-power verification

✔ Verify isolation, retention, and power gating

✔ Improve RTL verification confidence

✔ Develop practical debugging skills

✔ Prepare for advanced CPU and SoC verification

Register Today

Strong RTL verification forms the foundation of every successful low-power semiconductor design. This course provides the practical methodologies and verification techniques needed to confidently verify power-aware RTL implementations before integration into larger SoC environments.