Part 1 — Block-Level RTL Debug

2-session Live Online Training

Master the fundamentals of RTL debugging using industry-proven verification methodologies, simulation workflows, and formal verification techniques. This practical training equips engineers with the skills needed to identify, analyse, and resolve complex RTL design issues using the same structured approaches adopted by leading semiconductor companies.

Format: Live Online
Duration: 2 Consecutive sessions | 4 Hours per session
Pricing: $60

Register for Part 1

Whether you're building your verification career or looking to strengthen your RTL debugging expertise, this course provides practical, hands-on knowledge you can apply immediately to ASIC, FPGA, and SoC verification projects.

Course Overview

Build a strong foundation in modern RTL debugging by learning the structured methodologies, simulation techniques, and verification workflows used by professional ASIC and FPGA verification teams.

This intensive two-session training explores how engineers identify, analyse, reproduce, and eliminate design bugs at the RTL level using simulation, waveform analysis, assertions, coverage-driven verification, and formal verification techniques. Participants will gain practical experience with industry-standard debugging workflows while learning to isolate root causes and efficiently accelerate verification closure.

Whether working with UVM environments, formal verification tools, or large-scale regression suites, this course provides a practical framework for debugging increasingly complex digital designs with confidence.

What You Will Learn

By the end of this training, you will:

• Understand where debugging fits within the complete RTL verification lifecycle

• Learn a structured methodology for analysing and resolving design failures using the DARE Debug Loop

• Develop practical skills in simulation-based debugging using UVM logs and waveform analysis

• Identify and resolve X-propagation, assertion failures, deadlocks, and protocol violations

• Apply coverage-driven debugging techniques to improve regression efficiency

• Analyse formal verification counterexamples (CEX) and distinguish real, spurious, and vacuous failures

• Build efficient regression triage workflows using seed capture, replay, and minimisation techniques

• Learn professional debugging practices using commercial EDA tools and open-source alternatives

• Improve verification productivity through proven industry methodologies and best practices

Topics Covered

Session 1 — RTL Simulation Debug Foundations

• Understanding the digital verification flow and where debugging fits within the design lifecycle

• RTL bug taxonomy and structured bug classification

• The DARE Debug Loop (Detect, Analyse, Reproduce, Eliminate)

• Debugging using UVM logs and simulation reports

• Waveform tracing and root-cause analysis

• Simulation-based debugging workflows

• X-propagation analysis and resolution

• Assertion-Based Verification (SystemVerilog Assertions)

• Debugging protocol failures, deadlocks, and livelocks

• Practical debugging demonstrations using realistic RTL examples

Session 2 — Coverage-Driven & Formal Verification Debug

• Functional and code coverage analysis

• Coverage-driven debugging methodologies

• Regression triage and failure classification

• Seed capture, replay, and test case minimisation

• Introduction to formal verification workflows

• Counterexample (CEX) analysis and debug strategies

• Assume/Guarantee constraint debugging

• Formal reachability analysis

• Commercial EDA debugging workflows

• Open-source debugging tools and best-practice verification checklists

Who Should Attend

This course is ideal for:

• RTL Design Engineers

• ASIC Verification Engineers

• FPGA Engineers

• UVM Verification Engineers

• Formal Verification Engineers

• Graduate Verification Engineers

• SoC Design Engineers

• Hardware Design Engineers

• Digital IC Engineers

• Technical Leads responsible for RTL verification and debug

Training Format

• Live online instructor-led sessions

• Two consecutive training sessions

• Four hours of interactive instruction per session

• Hands-on debugging demonstrations

• Practical waveform and log analysis exercises

• Real-world RTL debugging case studies

• Commercial and open-source tool workflows

• Interactive Q&A and technical discussions

What's Included

• Live instructor-led training

• Comprehensive digital course materials

• Hands-on technical demonstrations

• Interactive Q&A sessions

• Certificate of Completion

Key Benefits

✔ Learn a structured methodology for debugging RTL designs efficiently

✔ Build confidence analysing simulation failures and waveform data

✔ Improve your ability to identify and isolate complex verification issues

✔ Understand how assertions, coverage, and formal verification complement simulation-based debugging

✔ Gain practical experience with professional verification workflows used across the semiconductor industry

✔ Learn debugging techniques that reduce regression turnaround time and improve verification quality

✔ Develop transferable debugging skills applicable to ASIC, FPGA, and SoC development projects

✔ Strengthen your ability to resolve design issues before silicon implementation