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Multi-Level Hardware Debug - Part 2 - CPU HW/SW Debug

Wed 14 Oct 2026 12:00 PM - Thu 15 Oct 2026 4:00 PM BST Online

Multi-Level Hardware Debug - Part 2 - CPU HW/SW Debug

Wed 14 Oct 2026 12:00 PM - Thu 15 Oct 2026 4:00 PM BST Online

Part 2 — CPU HW/SW Debug (Single-Core, Multi-Core & Application-Level)

2-session Live Online Training

Develop practical expertise in debugging modern processors by learning how hardware and software debugging techniques work together across single-core, multi-core, bare-metal, RTOS, and Linux environments. This hands-on training equips engineers with the knowledge and tools needed to efficiently diagnose complex CPU and embedded software issues using industry-standard debugging methodologies.

Format: Live Online
Duration: 2 Consecutive sessions | 4 Hours per session
Pricing: $60

Register for Part 2

Whether you're a verification engineer, embedded software developer, or SoC designer, this course provides practical debugging techniques you can apply immediately to processor development, firmware validation, and hardware/software integration projects.

Course Overview

Gain practical expertise in debugging modern processors by learning how hardware and software debugging techniques work together across single-core, multi-core, bare-metal, RTOS, and Linux environments.

This intensive two-session training explores the complete CPU hardware/software debug workflow, from understanding the architecture of modern debug modules and JTAG interfaces to using GDB, OpenOCD, and RISC-V debug technologies for real-world software and hardware troubleshooting.

Participants will learn how professional engineers debug processor behaviour, investigate firmware issues, diagnose race conditions, analyse exceptions, and resolve complex multi-core problems using industry-standard tools and proven debugging methodologies.

What You Will Learn

By the end of this training, you will:

  • Understand the architecture of modern CPU hardware and software debugging environments

  • Learn how GDB, OpenOCD, JTAG, and the RISC-V Debug Module work together during live debugging

  • Apply practical techniques for debugging firmware, applications, and processor hardware

  • Explore single-core and multi-core debugging methodologies

  • Diagnose race conditions, deadlocks, and synchronisation issues across multiple processor cores

  • Learn OS-aware debugging techniques for Bare-Metal, RTOS, and Linux systems

  • Understand hardware breakpoints, watchpoints, trigger modules, and debug registers

  • Analyse exceptions, stack overflows, memory corruption, and processor state

  • Build practical workflows for debugging complex embedded software running on modern processors

Topics Covered

Session 1 — CPU Hardware & Software Debug Foundations

  • Hardware versus software debugging concepts

  • Debug layers from software applications to processor hardware

  • JTAG fundamentals and Debug Transport Modules

  • RISC-V Debug Module architecture

  • OpenOCD and GDB integration

  • Software and hardware breakpoints

  • Watchpoints and trigger mechanisms

  • Abstract Commands, Program Buffer and System Bus Access

  • Register, memory, and processor state inspection

  • Practical CPU debugging demonstrations using simulated and hardware targets

Session 2 — Single-Core, Multi-Core & Application-Level Debug

  • Single-core debugging workflows

  • Register, memory, and call-stack analysis

  • Debugging exceptions and illegal instruction faults

  • Stack overflow detection and memory corruption analysis

  • Multi-core debugging methodologies

  • Race condition and deadlock diagnosis

  • Cross-triggering and halt groups

  • RTOS-aware debugging techniques

  • Linux application and kernel debugging fundamentals

  • Production firmware debugging and field diagnostics

Who Should Attend

This course is ideal for:

  • CPU Verification Engineers

  • Embedded Software Engineers

  • Firmware Engineers

  • Processor Architects

  • SoC Design Engineers

  • Hardware Bring-Up Engineers

  • Silicon Validation Engineers

  • FPGA Engineers working with embedded processors

  • Verification Engineers expanding into HW/SW co-debug

  • Technical Leads responsible for processor and embedded platform development

Training Format

  • Live online instructor-led sessions

  • Two consecutive training sessions

  • Four hours of interactive instruction per session

  • Live demonstrations using industry-standard debugging tools

  • Practical CPU debugging case studies

  • Hardware and software debugging workflows

  • Interactive technical discussions and Q&A

  • Real-world debugging scenarios drawn from modern processor development

What's Included

  • Live instructor-led training

  • Comprehensive digital course materials

  • Practical debugging demonstrations

  • Interactive Q&A sessions

  • Certificate of Completion

Key Benefits

✔ Learn how professional engineers debug modern processor architectures

✔ Gain confidence using GDB, OpenOCD, JTAG, and RISC-V debugging technologies

✔ Understand the interaction between processor hardware and embedded software during debugging

✔ Learn practical techniques for diagnosing firmware failures, exceptions, and memory issues

✔ Develop efficient workflows for debugging single-core and multi-core processor systems

✔ Improve your ability to investigate race conditions, deadlocks, and synchronisation problems

✔ Build practical skills applicable to ASIC, FPGA, embedded software, and SoC development

✔ Strengthen your expertise in modern CPU hardware/software co-debug methodologies