[6 sessions] Multicore Programming: Development and Verification Live Online Training Series

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the six sessions:
23 September 2026 – Day 1: Uniprocessor Foundations & Intro to Multicore Execution
29 September 2026 – Day 2: RISC-V Weak Memory Ordering (RVWMO) & Fuzzing
1 October 2026 – Day 3: Cache Coherency Protocols & Cache-Aware Software
16 October 2026 – Day 4: Multicore SoC Architecture & Interconnects
30 October 2026 – Day 5: Virtual Memory Hardware & Hypervisor Architecture
5 November 2026 – Day 6: Complete Application-Domain SoC Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS AT $250 ONLY

Overview

Modern computing relies heavily on multicore architectures, yet designing, programming, and verifying these complex chips present critical challenges in concurrency, memory consistency, and hardware bugs. This intensive 6-day technical course provides an end-to-end deep dive into multicore processor development using the open RISC-V ISA. Across 24 detailed modules, attendees will transition from single-core fundamentals to industrial-grade SoC verification, learning to detect race conditions, handle memory ordering, configure cache coherency, and achieve complete application-domain sign-off.

What You Will Learn

By the end of this programme, you will:

● Understand core microarchitectural pipelines and thread execution context (HARTs).
● Master the official RISC-V Weak Memory Ordering (RVWMO) specification.
● Utilize automated fuzzing pipelines (HARTBREAKER) to uncover hardware bugs.
● Implement hardware cache coherency protocols (MESI/MOESI) and cache-aware software.
● Configure system interconnects, PLIC/CLINT interrupt controllers, and coherent DMA.
● Manage hardware virtual memory, TLB shootdowns, and RISC-V Hypervisor extensions.
● Execute complete application-domain SoC sign-off and formal verification workflows.

Who Should Attend
● Digital Design & RTL Engineers
● Hardware Verification Engineers (UVM / Formal)
● Embedded Systems & Firmware Developers
● Computer Architecture Researchers & CPU Designers
● Systems Programmers transitioning into multicore hardware design

Key Benefits
● ✔ Master multicore processor architecture and memory models within one structured programme
● ✔ Uncover complex concurrency bugs using modern hardware fuzzing tools
● ✔ Progress from single-core foundations to full SoC tape-out sign-off methodologies
● ✔ Gain hands-on exposure to real-world RISC-V cores including BOOM, NaxRiscv, and XiangShan
● ✔ Follow an end-to-end industrial training structure designed for professional development