Multicore Programming - Day 1: Uniprocessor Foundations & Intro to Multicore Execution

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the six sessions:
23 September 2026 – Day 1: Uniprocessor Foundations & Intro to Multicore Execution
29 September 2026 – Day 2: RISC-V Weak Memory Ordering (RVWMO) & Fuzzing
1 October 2026 – Day 3: Cache Coherency Protocols & Cache-Aware Software
16 October 2026 – Day 4: Multicore SoC Architecture & Interconnects
30 October 2026 – Day 5: Virtual Memory Hardware & Hypervisor Architecture
5 November 2026 – Day 6: Complete Application-Domain SoC Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS AT $250 ONLY

Overview

Establish the fundamentals of the transition from uniprocessor execution to concurrent multicore systems. You will examine how multiple execution contexts (HARTs) interact with shared memory, explore hardware-level race conditions, and implement atomic primitives.

What You Will Learn

By the end of this module, you will:

● Understand core microarchitectural pipeline stages and control execution.
● Analyze HART execution contexts and thread scheduling primitives.
● Implement atomic memory operations and memory fencing techniques.
● Debug real-world concurrency bugs and hardware race conditions.

Who Should Attend

● Digital Design Engineers
● Firmware & Embedded Developers
● Hardware Verification Engineers
● Engineers transitioning into multicore CPU design

Topics Covered

Session 1
Module 1: Uniprocessor Microarchitecture Refresher
Module 2: Multicore Execution Contexts & HARTs
Module 3: Atomic Operations & Synchronization Primitives
Module 4: Concurrency Bugs & Race Condition Analysis
Hands-on Labs
HART execution tracing
Atomic lock implementation and race condition debugging

Key Benefits

•  ✔️ Build essential foundations in multicore microarchitecture
• ✔️ Learn practical synchronization and memory fencing techniques
• ✔️ Gain confidence in diagnosing low-level concurrency bugs