Multicore Programming - Day 2: RISC-V Weak Memory Ordering (RVWMO) & Fuzzing

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the six sessions:
23 September 2026 – Day 1: Uniprocessor Foundations & Intro to Multicore Execution
29 September 2026 – Day 2: RISC-V Weak Memory Ordering (RVWMO) & Fuzzing
1 October 2026 – Day 3: Cache Coherency Protocols & Cache-Aware Software
16 October 2026 – Day 4: Multicore SoC Architecture & Interconnects
30 October 2026 – Day 5: Virtual Memory Hardware & Hypervisor Architecture
5 November 2026 – Day 6: Complete Application-Domain SoC Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS AT $250 ONLY

Overview

Memory ordering is one of the most subtle sources of multicore failure. Day 2 explores the official RISC-V Weak Memory Ordering (RVWMO) specification and demonstrates automated hardware fuzzing to uncover hidden processor bugs.

What You Will Learn

By the end of this module, you will:

● Master the rules and constraints of the RVWMO memory model.
● Differentiate between Sequential Consistency and Weak Memory Ordering.
● Utilize the HARTBREAKER fuzzing pipeline for hardware verification.
● Analyze real-world bug case studies from BOOM, NaxRiscv, and XiangShan processors.

Who Should Attend

● Verification Engineers (Formal / Simulation)
● CPU Architects & RTL Engineers
● Systems Software Engineers

Topics Covered

Session 2

Module 5: Introduction to Memory Consistency Models
Module 6: Deep-Dive into RVWMO Specification
Module 7: Automated Fuzzing with HARTBREAKER
Module 8: Case Studies: Bugs in BOOM, NaxRiscv & XiangShan
Hands-on Labs & Demos
Automated memory consistency fuzzing pipeline with HARTBREAKER
Bug analysis on open-source RISC-V cores

Key Benefits

● ✔️ Master the complexities of the RVWMO specification
● ✔️Learn automated fuzzing methodologies for processor bug discovery
● ✔️ Analyze real industrial hardware bug case studies