Multicore Programming - Day 3: Cache Coherency Protocols & Cache-Aware Software

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the six sessions:
23 September 2026 – Day 1: Uniprocessor Foundations & Intro to Multicore Execution
29 September 2026 – Day 2: RISC-V Weak Memory Ordering (RVWMO) & Fuzzing
1 October 2026 – Day 3: Cache Coherency Protocols & Cache-Aware Software
16 October 2026 – Day 4: Multicore SoC Architecture & Interconnects
30 October 2026 – Day 5: Virtual Memory Hardware & Hypervisor Architecture
5 November 2026 – Day 6: Complete Application-Domain SoC Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS AT $250 ONLY

Overview

Maintaining data integrity across distributed caches requires specialized hardware protocols and software patterns. Day 3 focuses on cache coherency implementations and writing software optimized for hardware cache efficiency.

What You Will Learn

By the end of this module, you will:

● Understand state transitions in MESI and MOESI coherency protocols.
● Identify hardware cache snooping and directory-based coherence mechanisms.
● Eliminate performance bottlenecks caused by False Sharing in multicore code.
● Optimize memory layouts for cache line alignment and throughput.

Who Should Attend

● Embedded Software Engineers
● RTL & Cache Controller Designers
● High-Performance Systems Programmers

Topics Covered

Session 3
Module 9: Hardware Cache Coherency Fundamentals
Module 10: MESI & MOESI Protocol Walkthrough
Module 11: False Sharing & Software Bottlenecks
Module 12: Designing Cache-Aware Embedded Code
Hands-on Labs
Cache line profiling
Resolving False Sharing in C/C++ embedded applications

Key Benefits

● ✔️ Understand low-level MESI/MOESI state transitions
● ✔️Write software that maximizes hardware cache throughput
● ✔️Prevent costly false sharing performance penalties