Multicore Programming - Day 5: Virtual Memory Hardware & Hypervisor Architecture

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the six sessions:
23 September 2026 – Day 1: Uniprocessor Foundations & Intro to Multicore Execution
29 September 2026 – Day 2: RISC-V Weak Memory Ordering (RVWMO) & Fuzzing
1 October 2026 – Day 3: Cache Coherency Protocols & Cache-Aware Software
16 October 2026 – Day 4: Multicore SoC Architecture & Interconnects
30 October 2026 – Day 5: Virtual Memory Hardware & Hypervisor Architecture
5 November 2026 – Day 6: Complete Application-Domain SoC Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS AT $250 ONLY

Overview

Modern multicore operating systems rely on robust virtual memory and hardware-assisted virtualization. Day 5 covers Translation Lookaside Buffers (TLBs), page table management, and hypervisor execution contexts.

What You Will Learn

By the end of this module, you will:

● Understand hardware page table walks and multi-level page table setups.
● Manage TLB shootdowns and consistency across multiple processing cores.
● Explore the RISC-V Hypervisor (H-Extension) architecture.
● Configure two-stage address translation for virtualized environments.

Who Should Attend

● Hypervisor & OS Kernel Engineers
● CPU Hardware Engineers
● Systems Programmers & Virtualization Developers

Topics Covered

Session 5
Module 17: Virtual Memory Hardware & MMU Integration
Module 18: TLB Coherency & Multicore Shootdown Operations
Module 19: RISC-V Hypervisor Extension Architecture
Module 20: Two-Stage Address Translation & Guest Isolation
Hands-on Labs
Page table setup exercises
TLB shootdown tracing and hypervisor translation demo

Key Benefits

● ✔️ Master hardware MMU operations and TLB management
● ✔️ Understand RISC-V hardware virtualization primitives
● ✔️Build skills in kernel-level and hypervisor-level software development