Multicore Programming - Day 6: Complete Application-Domain SoC Sign-Off

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the six sessions:
23 September 2026 – Day 1: Uniprocessor Foundations & Intro to Multicore Execution
29 September 2026 – Day 2: RISC-V Weak Memory Ordering (RVWMO) & Fuzzing
1 October 2026 – Day 3: Cache Coherency Protocols & Cache-Aware Software
16 October 2026 – Day 4: Multicore SoC Architecture & Interconnects
30 October 2026 – Day 5: Virtual Memory Hardware & Hypervisor Architecture
5 November 2026 – Day 6: Complete Application-Domain SoC Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS AT $250 ONLY

Overview

The final phase of chip development is ensuring complete coverage and functional correctness before tape-out. Day 6 delivers a systematic framework for application-domain SoC sign-off across verification, validation, and compliance.

What You Will Learn

By the end of this module, you will:

● Define comprehensive SoC sign-off metrics and coverage goals.
● Apply formal verification techniques to multicore memory ordering and coherency.
● Execute architectural compliance tests for RISC-V platforms.
● Build robust post-silicon validation and debugging workflows.

Who Should Attend

● Lead Verification Engineers
● Hardware Sign-Off Managers
● SoC Integration & Validation Engineers

Topics Covered

Session 6
Module 21: Verification Strategies for Complex SoCs
Module 22: Formal Verification of Memory Models & Coherency
Module 23: RISC-V Architectural Compliance & Conformance
Module 24: Tape-Out Sign-Off Checklist & Best Practices
Hands-on Labs
Compliance suite execution
Formal assertion verification for memory coherency

Key Benefits

● ✔️ Learn complete tape-out sign-off methodologies
● ✔️ Gain hands-on exposure to formal memory model verification
● ✔️ Ensure architectural compliance for industrial RISC-V SoCs