Multicore Programming - Day 4: Multicore SoC Architecture & Interconnects

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the six sessions:
23 September 2026 – Day 1: Uniprocessor Foundations & Intro to Multicore Execution
29 September 2026 – Day 2: RISC-V Weak Memory Ordering (RVWMO) & Fuzzing
1 October 2026 – Day 3: Cache Coherency Protocols & Cache-Aware Software
16 October 2026 – Day 4: Multicore SoC Architecture & Interconnects
30 October 2026 – Day 5: Virtual Memory Hardware & Hypervisor Architecture
5 November 2026 – Day 6: Complete Application-Domain SoC Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS AT $250 ONLY

Overview

Connecting multiple processing cores requires high-bandwidth system interconnects and robust interrupt routing. Day 4 analyzes multicore SoC design, bus topologies, interrupt controllers, and DMA peripherals.

What You Will Learn

● Compare bus-based, crossbar, and Network-on-Chip (NoC) topologies.
● Configure RISC-V core interrupt structures using PLIC and CLINT.
● Implement coherent DMA transfers and manage memory access conflicts.
● Evaluate system throughput and bandwidth constraints under load.

Who Should Attend

● SoC Architects & Integration Engineers
● Device Driver & Board Support Package (BSP) Engineers
● Hardware Design Engineers

Topics Covered

Session 4
Module 13: System-on-Chip Interconnects & Topologies
Module 14: Interrupt Controllers: PLIC & CLINT Architecture
Module 15: Direct Memory Access (DMA) in Multicore Systems
Module 16: SoC Bus Arbitration & Bandwidth Optimization
Hands-on Labs
SoC Interconnect simulation
Configuring PLIC interrupt routing and coherent DMA setups

Key Benefits

● ✔️ Learn modern SoC bus topologies and arbitration schemes
● ✔️Understand hardware interrupt handling across multiple HARTs
● ✔️ Optimize system-level memory bandwidth and peripheral throughput