AI for RTL Design and Verification | Session 1: AI Methods in RTL and DV

AI for RTL Design and Verification | Session 1: AI Methods in RTL and DV

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This session explores AI methods for RTL design and design verification, including LLM and agent workflows, AI-assisted RTL, specification-to-UVM generation and the role of a trusted scoreboard.

The session includes a live demonstration using ScriptV1, Alpinum's configuration-driven Python UVM generator, to build and run a FIFO testbench.

This session is part of a 3-session professional training programme:

What You Will Learn

• LLM and agent workflows for RTL design and verification

• AI-assisted RTL design

• Specification-to-UVM generation

• The role of a trusted scoreboard

• Reinforcement learning and machine learning applications in PPA, coverage and regression selection

• How to inspect simulation results and identify a verification failure

Why This Matters

AI-generated testbenches need to be evaluated against actual design behaviour. A passing simulation does not necessarily mean that the testbench can expose a real RTL defect.

This session demonstrates how generated verification artifacts and scoreboard results can help engineers identify and investigate design faults.

Ideal For

• RTL designers

• Design verification engineers

• Verification leads

• Engineering managers assessing AI-assisted verification

Basic RTL and simulation knowledge is required. Familiarity with SystemVerilog or UVM is helpful.

Training Format

• 2-hour live online training session

• Concise teaching and live demonstrations

• FIFO testbench generation using ScriptV1

• Inspection of a passing simulation run

• Investigation of a pointer defect through the first scoreboard mismatch

• Application of the generator to RAM

This session is Session 1 of the 3-session AI for RTL Design and Verification Programme.