AI for RTL Design and Verification | Session 3: Tools, Deployment and Execution

AI for RTL Design and Verification | Session 3: Tools, Deployment and Execution

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This session explores how engineering teams can safely integrate AI-assisted verification into their toolchains. Topics include model selection, approved IP handling, retrieval-augmented generation (RAG) over specifications, simulator feedback, bounded retries, CI records and human approval.

The session includes a live demonstration of VerifAgent, MooresLab AI's commercial verification assistant, followed by a guided hands-on activity using AlpinumDV.

This session is part of a 3-session professional training programme:

• Session 1 — AI Methods in RTL and DV

• Session 2 — Benefits, Limitations and Evidence

• Session 3 — Tools, Deployment and Execution

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• Model selection for AI-assisted verification

• Approved IP handling

• RAG over design specifications

• Simulator feedback and bounded retries

• CI records and human approval

• Safe integration of AI verification workflows into engineering toolchains

• How to review verification plans, generated artifacts, simulation results and coverage evidence

Why This Matters

Deploying AI verification tools requires more than generating testbenches. Teams need a controlled workflow to handle design inputs, review generated outputs, evaluate simulator results, and decide when additional verification is necessary.

This session demonstrates a practical workflow for evaluating and improving AI-assisted verification results.

Ideal For

• RTL designers

• Design verification engineers

• Verification leads

• Engineering managers assessing AI deployment

• Teams exploring AI-assisted verification for IP projects

Basic RTL and simulation knowledge is required. Familiarity with SystemVerilog or UVM is helpful.

Training Format

• 2-hour live online training session

• Concise teaching and live demonstrations

• VerifAgent demonstration using an ALU or FIFO example

• Guided hands-on activity using AlpinumDV

• Review of generated verification plans and artifacts

• Simulation and coverage inspection

• Identification of a coverage gap or failure, followed by a rerun and evidence comparison

The guided hands-on activity uses a prepared design and an approved tool environment arranged before delivery.

This session is Session 3 of the 3-session AI for RTL Design and Verification Programme.