Formal Verification | Session 1: Formal Foundations, SVA and First Proofs

Formal Verification | Session 1: Formal Foundations, SVA and First Proofs

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This session introduces formal verification from first principles, exploring how formal proofs differ from simulation and how to write properties and constraints to verify RTL design behaviour.

You will learn SystemVerilog Assertions (SVA), work with sequences and advanced assertion operators, and investigate how to prove properties and interpret the results.

This session is part of a 3-session professional training programme:

• Session 1 — Formal Foundations, SVA and First Proofs

• Session 2 — Complex Proofs, Signoff and Block-Level Formal

• Session 3 — Formal Reuse, Advanced Formal and AI

REGISTRATION FOR ALL 3 SESSIONS IS 100$ ONLY.

What You Will Learn

• Why formal verification is used and how it differs from simulation

• Properties, constraints, assumptions and coverage

• SVA syntax and sequences

• Writing properties for formal verification and simulation

• Proving a basic property and interpreting the results

• Advanced SVA operators

• Writing complex assertions

Why This Matters

Formal verification requires well-defined properties and constraints to establish whether a design satisfies its intended behaviour.

This session develops the foundations needed to write meaningful assertions, understand proof results and progress towards more complex verification problems.

Ideal For

• RTL designers

• Design verification engineers

• Formal verification engineers beginning with formal methods

• Verification leads seeking a stronger understanding of SVA

Basic RTL and simulation knowledge is required. Familiarity with SystemVerilog is helpful, but no prior formal verification experience is needed.

Training Format

• 3-hour live online training session

• Concise teaching modules

• Live synchronous FIFO and ALU design examples

• X-Propagation and Reachability App demonstrations

• Three-question quiz after every module

• Online submission exercises corresponding to the demonstrations

• Breaks for quiz review and submissions

• Overnight quiz

This session is Session 1 of the 3-session Formal Verification: Properties, Proofs and Signoff Programme.