Formal Verification | Session 2: Complex Proofs, Signoff and Block-Level Formal

Formal Verification | Session 2: Complex Proofs, Signoff and Block-Level Formal

We offer a 50% discount to students; please complete this form to avail the discount.

This session focuses on developing complex formal proofs, improving convergence, debugging failing properties and determining when verification is complete.

You will explore assertion quality, FSM protocols, abstraction, formal signoff metrics and full formal verification at block level, including the differences between Sequential Equivalence Checking (SEC) and Logic Equivalence Checking (LEC).

This session is part of a 3-session professional training programme:

• Session 1 — Formal Foundations, SVA and First Proofs

• Session 2 — Complex Proofs, Signoff and Block-Level Formal

• Session 3 — Formal Reuse, Advanced Formal and AI

REGISTRATION FOR ALL 3 SESSIONS IS 100$ ONLY.

What You Will Learn

• Local variables and FSM protocols

• Assertion quality

• Complex proof setup and convergence

• Abstraction techniques

• Debugging failing properties

• Formal signoff metrics

• Full formal verification of a block

• SEC versus LEC

• Formal verification within the design flow

• The AHAA model and formal verification for designers

Why This Matters

Complex properties can be difficult to prove, and a failed proof requires careful investigation before the underlying design behaviour can be understood.

This session develops practical methods for setting up proofs, investigating failures, improving convergence and evaluating formal signoff evidence.

Ideal For

• RTL designers

• Design verification engineers

• Formal verification engineers

• Verification leads working with complex proofs and signoff

Basic RTL and simulation knowledge is required. Familiarity with SystemVerilog is helpful.

Training Format

• 3-hour live online training session

• Concise teaching modules

• Live up/down counter, two-transaction FIFO and SelAB examples

• Formal Coverage Analyzer demonstration

• Connectivity Checking demonstration

• Formal Low Power demonstration

• Formal Testbench Analyzer demonstration

• Three-question quiz after every module

• Online submission exercises, breaks and overnight quiz

This session is Session 2 of the 3-session Formal Verification: Properties, Proofs and Signoff Programme.