[3 sessions] RISC-V Verification: From Block to SoC

[3 sessions] RISC-V Verification: From Block to SoC

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This 3-session professional training programme covers RISC-V verification at three levels: the individual RTL block, the complete CPU core, and the full System-on-Chip (SoC).

Each session combines concise teaching with three live demonstrations using the CVA6 core, Spike/RISC-V-DV, RISC-V compliance suites, OpenPiton and Chipyard.

The programme consists of three sessions:

• Session 1 — Block-Level Verification

• Session 2 — CPU-Level Verification

• Session 3 — SoC-Level Verification

What You Will Learn

By the end of this programme, you will:

• Apply block-level UVM and formal testbench methodologies

• Develop behaviour-table-driven test plans and corner-case tests

• Design and close block-level coverage against sign-off criteria

• Use retirement-based checking and understand CPU verification abstraction levels

• Investigate hazards, forwarding and memory ordering

• Generate instruction streams using RISC-V-DV and debug with Spike

• Run RISC-V compliance suites and compare VCS and Xcelium log traces

• Verify SoC integration, reset, boot, clock and interrupt wiring

• Explore firmware and OS boot, resilience, scaling and sign-off

• Check memory consistency and cache coherence against a formal model

Why This Matters

Verifying an individual block is only one part of establishing confidence in a RISC-V implementation. Verification must also cover complete CPU behaviour and the processor's integration into a full SoC.

This programme demonstrates how verification methods and evidence evolve from block-level proofs to CPU-level checking and full-SoC verification.

Ideal For

• Verification engineers working with RISC-V implementations

• Engineers interested in block, CPU and SoC verification

• Engineers seeking practical experience with UVM, formal verification and RISC-V tools

Participants should have working knowledge of UVM and basic RISC-V ISA concepts.

Training Format

• 3 sessions

• 3 hours per session

• 9 hours in total

• Live online training

• 9 live demonstrations

• Three demonstrations per session

• Five-minute quiz and ten-minute break at the midpoint of each session

• Course materials and quiz discussions

The demonstrations use the CVA6 RISC-V core and the OpenPiton and Chipyard platforms.