RISC-V Verification | Session 1: Block-Level Verification

RISC-V Verification | Session 1: Block-Level Verification

We offer a 50% discount to students; please complete this form to avail the discount.

This session focuses on verifying individual RTL blocks within a RISC-V core before they are integrated into the complete chip.

You will explore block-level UVM and formal testbench methodologies, behaviour-table-driven test planning, corner-case design and block-level coverage closure and sign-off criteria.

This session is part of a 3-session professional training programme:

• Session 1 — Block-Level Verification

• Session 2 — CPU-Level Verification

• Session 3 — SoC-Level Verification

REGISTRATION FOR ALL 3 SESSIONS IS 100$ ONLY.

What You Will Learn

• Block-level UVM and formal testbench methodology

• Behaviour-table-driven test planning

• Corner-case test design

• Block-level coverage design and closure

• Formal verification and sign-off criteria

• Verification of illegal instruction encodings

• Misaligned memory accesses and address-translation overflow

• Atomic memory operations and formal ISA proofs

Why This Matters

Individual RTL blocks must be verified before they are integrated into a complete processor. Effective block-level verification requires deliberate test planning, corner-case analysis, coverage closure and evidence that the block behaves as intended.

This session demonstrates these methods using real blocks from the CVA6 RISC-V core.

Ideal For

• RISC-V verification engineers

• RTL designers

• Design verification engineers

• Engineers working with UVM and formal verification

Working knowledge of UVM and basic RISC-V ISA concepts is required.

Training Format

• 3-hour live online training session

• Concise teaching and methodology blocks

• Three live demonstrations using CVA6

• UVM and formal verification of the compressed decoder's illegal-encoding handling

• Load-store unit verification covering misaligned accesses, address-translation overflow and atomic memory operations

• Main decoder full-ISA formal proof across base, atomic and floating-point extensions

• Five-minute quiz and ten-minute break at the midpoint

• Course materials and quiz discussion

This session is Session 1 of the 3-session RISC-V Verification: From Block to SoC Programme.