RISC-V Verification | Session 2: CPU-Level Verification

RISC-V Verification | Session 2: CPU-Level Verification

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This session explores how to verify the behaviour of a complete RISC-V CPU after individual blocks have been verified.

You will cover retirement-based checking, abstraction levels, hazards, forwarding and memory ordering, supported by live demonstrations using RISC-V-DV, Spike, RISC-V compliance suites, VCS and Xcelium.

This session is part of a 3-session professional training programme:

• Session 1 — Block-Level Verification

• Session 2 — CPU-Level Verification

• Session 3 — SoC-Level Verification

REGISTRATION FOR ALL 3 SESSIONS IS 100$ ONLY.

What You Will Learn

• Retirement-based checking

• CPU verification abstraction levels

• Hazards and forwarding

• Memory ordering at CPU level

• Instruction-stream generation using RISC-V-DV

• Debugging with Spike

• RISC-V compliance testing

• VCS and Xcelium log-trace comparison

• Memory ordering across real RISC-V HARTs

Why This Matters

A processor must execute and retire instructions correctly, even when hazards, forwarding, and memory-ordering behaviour create complex interactions.

This session demonstrates how golden-model checking, compliance testing and shared-memory execution can help evaluate CPU behaviour.

Ideal For

• RISC-V verification engineers

• CPU design verification engineers

• Engineers working with instruction-level verification

• Verification engineers interested in compliance testing and memory ordering

Working knowledge of UVM and basic RISC-V ISA concepts is required.

Training Format

• 3-hour live online training session

• Concise teaching and methodology blocks

• Three live demonstrations

• Instruction-stream generation using RISC-V-DV and Spike debug

• RISC-V compliance suites with VCS and Xcelium log-trace comparison

• Parallel shared-memory execution across real RISC-V HARTs

• Five-minute quiz and ten-minute break at the midpoint

• Course materials and quiz discussion

This session is Session 2 of the 3-session RISC-V Verification: From Block to SoC Programme.