RISC-V Verification | Session 3: SoC-Level Verification

RISC-V Verification | Session 3: SoC-Level Verification

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This session explores how verification changes when a verified RISC-V CPU is integrated into a complete System-on-Chip (SoC).

You will cover SoC integration, reset, boot, clock and interrupt wiring, firmware and OS boot, resilience, scaling and sign-off. Live demonstrations use Chipyard, RocketChip-based SoC simulation, directed and Torture-generated instruction-stream tests, and formal memory-consistency checking.

This session is part of a 3-session professional training programme:

• Session 1 — Block-Level Verification

• Session 2 — CPU-Level Verification

• Session 3 — SoC-Level Verification

REGISTRATION FOR ALL 3 SESSIONS IS 100$ ONLY.

What You Will Learn

• SoC integration and verification

• Reset, boot, clock and interrupt wiring

• Firmware and operating-system boot

• Resilience, scaling and sign-off

• Building and simulating a RocketChip-based SoC using Chipyard

• Verifying a CPU inside a complete SoC

• Directed and Torture-generated instruction-stream tests

• Memory-consistency and cache-coherence checking

• Formal models and generated litmus tests

Why This Matters

A verified CPU can behave differently when integrated into a complete SoC, where reset, boot, interrupts, memory systems and other components must work together correctly.

This session demonstrates how to extend verification from CPU-level behaviour to full-SoC integration, memory consistency and cache coherence.

Ideal For

• RISC-V verification engineers

• SoC design verification engineers

• Engineers working on processor integration

• Verification engineers interested in system-level testing and formal memory-consistency checks

Working knowledge of UVM and basic RISC-V ISA concepts is required.

Training Format

• 3-hour live online training session

• Concise teaching and methodology blocks

• Three live demonstrations

• Building and simulating a RocketChip-based SoC in Chipyard

• Directed and Torture-generated instruction-stream tests

• Formal memory-consistency and cache-coherence checking using generated litmus tests

• Five-minute quiz and ten-minute break at the midpoint

• Course materials and quiz discussion

This session is Session 3 of the 3-session RISC-V Verification: From Block to SoC Programme.