SystemVerilog Assertions | Session 2: Properties, Sequences and Auxiliary Logic

SystemVerilog Assertions | Session 2: Properties, Sequences and Auxiliary Logic

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This session explores how to express complex timing and protocol rules through properties that remain correct and readable.

You will cover property semantics, sampling and evaluation regions, vacuous success, parameterised properties, advanced sequence operators, auxiliary logic and bind-based checkers. The live demonstrations use an ALU and the Unreachable App in VC Formal or Jasper to identify coverage targets that can never be hit.

This session is part of a 3-session professional training programme:

• Session 1 — Fundamentals of SVA

• Session 2 — Properties, Sequences and Auxiliary Logic

• Session 3 — Reuse, Formal Signoff and RISC-V

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• Property semantics and evaluation regions

• Sampling and vacuous success

• Multiple property endings

• Parameterised properties and generate constructs

• Repetition operators: [*], [=] and [->]

• Sequence operators: or, and, intersect, first_match, throughout and within

• Auxiliary logic and bind-based checkers

• $onehot, mutex and race avoidance

Why This Matters

Complex design protocols require assertions that accurately represent timing relationships and expected behaviour. Poorly constructed properties can be difficult to interpret or may not check what the engineer intended.

This session develops practical techniques for writing complex properties and investigating unreachable coverage targets.

Ideal For

• Design verification engineers

• RTL designers developing advanced SVA skills

• Formal verification engineers

• Verification leads working with complex properties and protocols

Familiarity with SystemVerilog RTL and simulation is required.

Training Format

• 2-hour live online training session

• Concise teaching blocks

• Live ALU verification using assumptions, assertions and reference-model properties.

• Unreachable App demonstration in VC Formal or Jasper

• Two five-minute forms

• Ten-minute break

• Overnight form covering the ALU assumptions, assertions and reference-model checks

This session is Session 2 of the 3-session SystemVerilog Assertions in Simulation and Formal Programme.