SystemVerilog Assertions | Session 3: Reuse, Formal Signoff and RISC-V

SystemVerilog Assertions | Session 3: Reuse, Formal Signoff and RISC-V

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This session focuses on reusing assertions across simulation and formal verification, understanding formal signoff metrics and evaluating whether a set of assertions is complete enough to sign off a design.

You will explore local variables, SVA limitations and performance, specification quality, grey-box checks, cone-of-influence coverage, fixed points, bound analysis and quality of formal verification (QoFV).

The live demonstrations follow an RV32I RISC-V CPU case study using VC Formal or Jasper, the Formal Coverage Analyzer and an AI tool for mapping assertions to requirements.

This session is part of a 3-session professional training programme:

• Session 1 — Fundamentals of SVA

• Session 2 — Properties, Sequences and Auxiliary Logic

• Session 3 — Reuse, Formal Signoff and RISC-V

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• Local variables and advanced SVA considerations

• SVA limitations and performance

• Specification quality and grey-box checks

• Reusing assertions across simulation and formal verification

• Formal verification metrics

• Cone-of-influence coverage

• Fixed points and bound analysis

• Quality of formal verification (QoFV)

• Measuring proof completeness

• Mapping assertions to requirements using an AI tool

Why This Matters

A successful proof does not automatically prove a design is fully verified. Engineers need to assess whether the assertions are sufficient, whether relevant coverage targets have been addressed and whether the available evidence supports signoff.

This session demonstrates how formal coverage analysis and requirement mapping help evaluate the completeness of a verification effort.

Ideal For

• Design verification engineers

• RTL designers developing reusable assertions

• Formal verification engineers

• Verification leads assessing formal signoff and proof completeness

Familiarity with SystemVerilog RTL and simulation is required. Prior assertion or formal verification experience is helpful but not required.

Training Format

• 2-hour live online training session

• Concise teaching blocks

• RV32I RISC-V CPU case study using VC Formal or Jasper

• Formal Coverage Analyzer demonstration

• AI-assisted SVA-to-requirement mapping

• Two five-minute forms

• Ten-minute break

• Overnight form covering the RISC-V case study and formal results

This session is Session 3 of the 3-session SystemVerilog Assertions in Simulation and Formal Programme.