SystemVerilog for Design and Verification | Session 1: Introduction to SystemVerilog

SystemVerilog for Design and Verification | Session 1: Introduction to SystemVerilog

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This session introduces SystemVerilog and explains how it extends Verilog for modern RTL design and verification. You will explore data types, procedural blocks, operators, interfaces, modports, tasks, functions, arrays and clocking blocks.

The live demonstrations use a FIFO built with SystemVerilog interfaces and an ALU driven through a clocking block, showing how input and output skew help prevent sampling races.

This session is part of a 3-session professional training programme:

• Session 1 — Introduction to SystemVerilog

• Session 2 — Classes, Randomisation and Coverage

• Session 3 — Assertions, DPI and Reuse

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• Data types and literals

• Procedural blocks: always_comb, always_ff and always_latch

• Blocking and non-blocking assignments

• Operators and user-defined types

• Interfaces and modports

• Hierarchy and connectivity

• Tasks and functions

• Arrays and clocking blocks

• Input and output skew and race avoidance

Why This Matters

SystemVerilog provides constructs that help engineers develop clearer RTL and more reliable testbenches.

This session establishes the language foundations needed to work with interfaces, clocking blocks and more advanced verification techniques.

Ideal For

• RTL designers moving from Verilog

• Design verification engineers

• Graduates entering verification

• Engineers preparing for UVM or SVA training

Working knowledge of Verilog and digital design is required. No prior SystemVerilog experience is needed.

Training Format

• 2-hour live online training session

• Concise teaching blocks

• Two live demonstrations using FIFO and ALU designs

• FIFO development using SystemVerilog interfaces

• ALU stimulus through a clocking block

• Two five-minute quizzes

• Ten-minute break

• Five-minute closing Q&A

This session is Session 1 of the 3-session SystemVerilog for Design and Verification Programme.