SystemVerilog for Design and Verification | Session 3: Assertions, DPI and Reuse

SystemVerilog for Design and Verification | Session 3: Assertions, DPI and Reuse

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This session explores how assertions, C integration and reusable verification components can improve debugging and reduce the effort required to repeat verification.

You will cover queues, dynamic and associative arrays, assertion-based verification, SVA sequences and properties, the Direct Programming Interface (DPI-C), debug and regression triage, and reuse through UVM, VIP and Portable Stimulus.

The live demonstrations extend an interface-based FIFO with SVA checks, then connect C code to an ALU testbench through DPI.

This session is part of a 3-session professional training programme:

• Session 1 — Introduction to SystemVerilog

• Session 2 — Classes, Randomisation and Coverage

• Session 3 — Assertions, DPI and Reuse

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• Queues, dynamic arrays and associative arrays

• Assertion-based verification

• SVA sequences and properties

• The Direct Programming Interface (DPI-C)

• Debug and regression triage

• Reuse through UVM and VIP

• Portable Stimulus

• AI applications across the verification flow

• Reusable assertions and verification components

Why This Matters

Effective verification requires more than generating stimulus. Engineers also need to check expected behaviour, investigate failures, integrate external code and reuse verification assets across projects.

This session demonstrates how SVA and DPI-C can extend existing testbenches and introduces approaches to verification reuse in modern design flows.

Ideal For

• RTL designers moving from Verilog to SystemVerilog

• Design verification engineers

• Engineers preparing for UVM or SVA training

• Verification engineers interested in DPI-C and reusable verification components.

Working knowledge of Verilog and digital design is required. No prior SystemVerilog experience is needed to begin the programme.

Training Format

• 2-hour live online training session

• Concise teaching blocks

• Two live demonstrations using FIFO and ALU designs

• Extending an interface-based FIFO with SVA checks

• Calling C code from an ALU testbench through DPI

• Two five-minute quizzes

• Ten-minute break

• Five-minute closing Q&A

This session is Session 3 of the 3-session SystemVerilog for Design and Verification Programme.