[3 sessions] Building UVM Testbenches

[3 sessions] Building UVM Testbenches

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This 3-session professional training programme introduces the Universal Verification Methodology (UVM), from understanding the class library to building multi-agent testbenches and reusable verification components.

The programme progresses from testbench structure and configuration to sequences, scoreboards, and test selection, then explores multiple agents, reusable UVM Verification Components (UVCs), and AI-assisted UVM generation. Each session combines concise teaching with live demonstrations using an ALU, a multi-port memory controller, an SPI interface and a FIFO.

The programme consists of three sessions:

• Session 1 — Introduction to UVM

• Session 2 — Building a UVM Testbench

• Session 3 — Advanced UVM Testbenches

What You Will Learn

By the end of this programme, you will:

• Understand the UVM library, methodology and component hierarchy

• Structure a UVM testbench and understand its directory layout

• Work with UVM components, objects, TLM and the factory

• Understand UVM phases, virtual interfaces and configuration

• Develop sequence items, sequences and sequencers

• Apply test selection and scoreboarding

• Use basic UVM debugging features

• Build testbenches with multiple agents and reusable UVCs

• Explore AI-assisted UVM generation

Why This Matters

UVM provides a structured methodology for building reusable and scalable verification environments. Understanding its components, sequences, scoreboards and configuration mechanisms helps engineers move from directed testbenches towards systematic verification.

This programme demonstrates how a UVM environment grows from a single ALU agent to a multi-agent SPI testbench, including an AI-generated FIFO testbench.

Ideal For

• Design verification engineers new to UVM

• Engineers moving from directed SystemVerilog testbenches

• RTL designers who need to read and debug UVM

• Verification leads

Working knowledge of SystemVerilog, including classes and interfaces, and basic simulation experience are required. Object-oriented programming familiarity is helpful.

Training Format

• 3 sessions

• 2 hours per session

• 6 hours in total

• Live online training

• 4 live demonstrations

• Short quizzes in every session

• Practical examples using ALU, multi-port memory controller, SPI and FIFO designs

• Course materials for all three sessions

Participants need a laptop and a stable internet connection.