Building UVM Testbenches | Session 1: Introduction to UVM

Building UVM Testbenches | Session 1: Introduction to UVM

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This session introduces the Universal Verification Methodology (UVM) and explains how its class library and methodology are used to structure a verification testbench.

You will explore the component hierarchy, objects, TLM, UVM classes, constructors, the factory, UVM phases, virtual interfaces and configuration. The live demonstration builds a UVM environment for an ALU, showing how its components, phases, factory and configuration connect to the design under test (DUT).

This session is part of a 3-session professional training programme:

• Session 1 — Introduction to UVM

• Session 2 — Building a UVM Testbench

• Session 3 — Advanced UVM Testbenches

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• The UVM library and methodology

• The class hierarchy of components and objects

• Transaction-Level Modelling (TLM)

• Testbench structure, packaging and directory layout

• UVM classes and the new constructor

• The UVM factory

• UVM phases

• Virtual interfaces and the top-level testbench

• Configuration basics

Why This Matters

A well-structured UVM environment depends on understanding how its components are created, configured and connected to the DUT.

This session establishes the foundations needed to build and maintain UVM testbenches before progressing to sequences, scoreboards and multiple agents.

Ideal For

• Design verification engineers new to UVM

• Engineers moving from directed SystemVerilog testbenches

• RTL designers who need to read and debug UVM

• Verification leads

Working knowledge of SystemVerilog, including classes and interfaces, and basic simulation experience are required. Object-oriented programming familiarity is helpful.

Training Format

• 2-hour live online training session

• Focused teaching blocks

• Live demonstration building a UVM environment for an ALU

• Practical exploration of components, phases, factory and configuration

• Five-minute quiz at the midpoint

• Ten-minute break with a quiz

• Live demonstration and further teaching

This session is Session 1 of the 3-session Building UVM Testbenches Programme.