Building UVM Testbenches | Session 2: Building a UVM Testbench

Building UVM Testbenches | Session 2: Building a UVM Testbench

We offer a 50% discount to students; please complete this form to avail the discount.

This session explores how sequences and scoreboards turn a UVM environment into a testbench that generates stimulus and checks results.

You will cover sequence items, sequences, sequencers, test selection, scoreboarding and basic UVM debugging features. The live demonstration applies these concepts to a multi-port memory controller.

This session is part of a 3-session professional training programme:

• Session 1 — Introduction to UVM

• Session 2 — Building a UVM Testbench

• Session 3 — Advanced UVM Testbenches

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• Sequence items

• Sequences and sequencers

• Test selection

• Scoreboarding

• Basic UVM debugging features

• Applying stimulus and checking results within a UVM testbench

Why This Matters

A UVM environment needs mechanisms to generate meaningful stimulus, select the right test, and verify that the DUT behaves correctly.

This session demonstrates how sequences and scoreboards support a practical verification flow using a multi-port memory controller.

Ideal For

• Design verification engineers new to UVM

• Engineers moving from directed SystemVerilog testbenches

• RTL designers who need to read and debug UVM

• Verification leads

Working SystemVerilog knowledge, including classes and interfaces, and basic simulation experience are required. Object-oriented programming familiarity is helpful.

Training Format

• 2-hour live online training session

• Focused teaching blocks

• Live demonstration using a multi-port memory controller

• Practical application of sequences, test selection and scoreboarding

• Five-minute quiz at the midpoint

• Ten-minute break with a quiz

• Live demonstration and further teaching

This session is Session 2 of the 3-session Building UVM Testbenches Programme.