Building UVM Testbenches | Session 3: Advanced UVM Testbenches

Building UVM Testbenches | Session 3: Advanced UVM Testbenches

We offer a 50% discount to students; please complete this form to avail the discount.

This session explores how UVM testbenches scale across multiple interfaces and how reusable verification components support more complex verification environments.

You will cover advanced interfaces for debugging, multiple agents, UVM Verification Components (UVCs) and AI-assisted UVM generation. The live demonstrations verify an SPI communication protocol using multiple agents, then show an AI UVM generator building a FIFO testbench.

This session is part of a 3-session professional training programme:

• Session 1 — Introduction to UVM

• Session 2 — Building a UVM Testbench

• Session 3 — Advanced UVM Testbenches

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• Advanced interfaces used for debugging

• Multiple-agent testbench architectures

• Reusable UVM Verification Components (UVCs)

• Scaling a testbench across several interfaces

• AI-assisted UVM generation

• Applying reusable components to protocol verification

• Understanding how AI generation can accelerate testbench creation

Why This Matters

As designs become more complex, verification environments need to support multiple interfaces and reusable components without becoming difficult to maintain.

This session shows how multi-agent testbenches and UVCs support reuse and how AI-assisted generation can help create verification environments.

Ideal For

• Design verification engineers

• Engineers moving from directed SystemVerilog testbenches

• RTL designers who need to read and debug UVM

• Verification leads

• Engineers interested in reusable verification components and AI-assisted UVM

Working SystemVerilog knowledge, including classes and interfaces, and basic simulation experience are required. Object-oriented programming familiarity is helpful.

Training Format

• 2-hour live online training session

• Focused teaching blocks

• Live SPI protocol verification using multiple agents

• AI UVM generator demonstration using a FIFO testbench

• Short quizzes

• Ten-minute break

• Practical demonstrations and discussion

This session is Session 3 of the 3-session Building UVM Testbenches Programme.