[4 sessions] Analog and Mixed-Signal Design and Verification — Intensive Track

[4 sessions] Analog and Mixed-Signal Design and Verification — Intensive Track

We offer a 50% discount to students; please complete this form to avail the discount.

This four-session professional training programme brings together four Alpinum courses in analog IC design, AMS languages and verification, real-number modeling, co-simulation, and power-aware verification.

Each course is condensed into a single three-hour session, combining concise teaching with three live demonstrations and short quizzes. The programme progresses from Python-based analog transistor sizing to AMS language modeling, UVM-based co-simulation and power-aware verification using UPF.

The programme consists of four sessions:

• Session 1 — Analog IC Design using Python: GM/ID Methodology

• Session 2 — Verilog-AMS, SystemVerilog-AMS & UVM-AMS

• Session 3 — AMS Co-Simulation (RNM & UVM)

• Session 4 — AMS Co-Simulation (Power-Aware / UPF)

What You Will Learn

By the end of this programme, you will:

• Apply the GM/ID methodology to analog IC design using Python

• Generate GM/ID curves and analyse parasitic capacitance

• Understand Verilog-AMS, SystemVerilog-AMS and UVM-AMS

• Model analog behaviour and connect mixed-signal components

• Explore real-number modeling (RNM) and UVM-based co-simulation

• Understand SPICE and Verilog-A modeling basics

• Integrate UVM-RNM testbenches and debug mixed-signal waveforms

• Apply UPF power intent, isolation and level shifting

• Investigate X-corruption and convergence in power-aware UVM environments

Why This Matters

Analog and mixed-signal design and verification require an understanding of transistor-level design, behavioral modeling, digital verification and power intent.

This intensive programme brings these topics together through practical demonstrations, providing a condensed refresher of the core concepts and workflows from four Alpinum courses.

Ideal For

• Analog and mixed-signal design engineers

• AMS verification engineers

• Design verification engineers working with UVM

• Engineers working with real-number modeling and co-simulation

• Engineers interested in power-aware verification and UPF

Prior exposure to the corresponding full-length courses is helpful but not required. Each session begins with a short refresher block.

Training Format

• 4 sessions

• 3 hours per session

• 12 hours in total

• Live online training

• 12 live demonstrations across the programme

• Four condensed teaching blocks per session

• Short quizzes after each taught block

• A break at the midpoint

• Ten-minute closing Q&A per session

• Course materials covering all four courses

Participants need a laptop and a stable internet connection.