Analog and Mixed-Signal Design | Session 1: Analog IC Design using Python — GM/ID Methodology

Analog and Mixed-Signal Design | Session 1: Analog IC Design using Python — GM/ID Methodology

We offer a 50% discount to students; please complete this form to avail the discount.

This session explores the GM/ID methodology for analog IC design and how a Python-based flow can help engineers understand transistor behaviour and size analog building blocks.

You will cover inversion regions, design curves and trade-offs involving gain, speed, noise and area, as well as Python lookup-table (LUT) workflows and parasitic capacitance extraction. The live demonstrations build the Python/LUT environment, generate GM/ID curves and parasitic-capacitance graphs, and size the input pair of a fully differential folded-cascode OTA.

This session is part of a 4-session professional training programme:

• Session 1 — Analog IC Design using Python: GM/ID Methodology

• Session 2 — Verilog-AMS, SystemVerilog-AMS & UVM-AMS

• Session 3 — AMS Co-Simulation (RNM & UVM)

• Session 4 — AMS Co-Simulation (Power-Aware / UPF)

REGISTRATION FOR ALL 4 SESSIONS IS 150$ ONLY.

What You Will Learn

• The transition from classical sizing to GM/ID

• Transistor behaviour and inversion regions

• Design curves and trade-offs involving gain, speed, noise and area

• Python-based lookup-table (LUT) environments

• Parasitic capacitance extraction

• Generating GM/ID curves with Python

• Applying a Python-driven sizing flow to an OTA

Why This Matters

Analog transistor sizing involves trade-offs between performance, noise and area. The GM/ID methodology and Python-based analysis provide a structured way to explore these trade-offs and support sizing decisions.

This session demonstrates how the methodology can be applied to a practical fully differential folded-cascode OTA.

Ideal For

• Analog IC design engineers

• Mixed-signal design engineers

• Engineers interested in transistor sizing and Python-based design flows

• Engineers seeking a refresher in analog design methodology

Prior exposure to the corresponding full-length course is helpful but not required.

Training Format

• 3-hour live online training session

• Four condensed teaching blocks

• Three live demonstrations

• Building the Python/LUT environment

• Generating GM/ID curves and parasitic-capacitance graphs

• Sizing the input pair of a fully differential folded-cascode OTA

• Short quizzes after each taught block

• Midpoint break and ten-minute closing Q&A

This session is Session 1 of the 4-session Analog and Mixed-Signal Design and Verification — Intensive Track.