Analog and Mixed-Signal Design | Session 2: Verilog-AMS, SystemVerilog-AMS & UVM-AMS

Analog and Mixed-Signal Design | Session 2: Verilog-AMS, SystemVerilog-AMS & UVM-AMS

We offer a 50% discount to students; please complete this form to avail the discount.

This session explores how Verilog-AMS, SystemVerilog-AMS and UVM-AMS work together to model, connect and verify mixed-signal designs.

You will cover Verilog-AMS fundamentals, Verilog-A behavioural modeling, the SystemVerilog-AMS object model, connectivity and Supernet architecture, adapters, master representation and UVM-AMS verification components.

The live demonstrations model and simulate an RC circuit in Verilog-A, connect a SAR ADC through a SystemVerilog-AMS real-number model for co-simulation, and verify an analog DUT using UVM-AMS concepts.

This session is part of a 4-session professional training programme:

• Session 1 — Analog IC Design using Python: GM/ID Methodology

• Session 2 — Verilog-AMS, SystemVerilog-AMS & UVM-AMS

• Session 3 — AMS Co-Simulation (RNM & UVM)

• Session 4 — AMS Co-Simulation (Power-Aware / UPF)

REGISTRATION FOR ALL 4 SESSIONS IS 150$ ONLY.

What You Will Learn

• Verilog-AMS fundamentals

• Verilog-A behavioural modeling

• The SystemVerilog-AMS object model

• Connectivity and Supernet architecture

• Adapters and master representation

• UVM-AMS fundamentals and architecture

• UVM-AMS verification components

• Workflow and migration considerations

Why This Matters

Mixed-signal verification requires analog and digital models to interact correctly within a common verification environment.

This session shows how AMS language features, real-number modeling, and UVM-AMS concepts support modeling, connectivity, and end-to-end verification.

Ideal For

• Analog and mixed-signal design engineers

• AMS verification engineers

• Design verification engineers working with UVM

• Engineers interested in behavioral modeling and mixed-signal co-simulation

Prior exposure to the corresponding full-length course is helpful but not required.

Training Format

• 3-hour live online training session

• Four condensed teaching blocks

• Three live demonstrations

• RC circuit modeling and simulation using Verilog-A

• SAR ADC co-simulation using a SystemVerilog-AMS real-number model

• Analog DUT verification using UVM-AMS concepts

• Short quizzes after each taught block

• Midpoint break and ten-minute closing Q&A

This session is Session 2 of the 4-session Analog and Mixed-Signal Design and Verification — Intensive Track.