Analog and Mixed-Signal Design | Session 3: AMS Co-Simulation (RNM & UVM)

Analog and Mixed-Signal Design | Session 3: AMS Co-Simulation (RNM & UVM)

We offer a 50% discount to students; please complete this form to avail the discount.

This session explores how SPICE-accurate models, real-number modeling (RNM) and UVM work together in an AMS co-simulation flow.

You will cover SystemVerilog and Verilog-AMS syntax, SPICE and Verilog-A modeling basics, VCS-AD compilation mechanics, power-aware AMS concepts, SV-RNM fundamentals, UVM-AMS agent interfacing, the mixed-signal bridge and UVM-RNM testbench integration.

The live demonstrations cover designing a CMOS inverter using a process design kit (PDK), simulating a comparator built on SV-RNM, and debugging an interactive mixed-signal waveform in Verdi through a UVM-RNM testbench.

This session is part of a 4-session professional training programme:

• Session 1 — Analog IC Design using Python: GM/ID Methodology

• Session 2 — Verilog-AMS, SystemVerilog-AMS & UVM-AMS

• Session 3 — AMS Co-Simulation (RNM & UVM)

• Session 4 — AMS Co-Simulation (Power-Aware / UPF)

REGISTRATION FOR ALL 4 SESSIONS IS 150$ ONLY.

What You Will Learn

• SystemVerilog and Verilog-AMS syntax

• SPICE and Verilog-A modeling basics

• VCS-AD compilation mechanics

• Power-aware AMS concepts

• SystemVerilog real-number modeling (SV-RNM)

• UVM-AMS agent interfacing

• The mixed-signal bridge

• UVM phasing and UVM-RNM testbench integration

• Mixed-signal waveform debugging in Verdi

Why This Matters

AMS co-simulation brings analog behavior and digital verification together. Understanding the models, interfaces, and testbench integration is important for investigating mixed-signal interactions and debugging simulation results.

This session demonstrates a practical flow from transistor-level modeling to real-number simulation and UVM-based waveform analysis.

Ideal For

• AMS verification engineers

• Analog and mixed-signal design engineers

• Design verification engineers working with UVM

• Engineers interested in RNM, SPICE-based models and mixed-signal debugging

Prior exposure to the corresponding full-length course is helpful but not required.

Training Format

• 3-hour live online training session

• Four condensed teaching blocks

• Three live demonstrations

• CMOS inverter design using a PDK

• Comparator simulation using SV-RNM

• Interactive mixed-signal waveform debugging using a UVM-RNM testbench in Verdi.

• Short quizzes after each taught block

• Midpoint break and ten-minute closing Q&A

This session is Session 3 of the 4-session Analog and Mixed-Signal Design and Verification — Intensive Track.