Analog and Mixed-Signal Design | Session 4: AMS Co-Simulation (Power-Aware / UPF)

Analog and Mixed-Signal Design | Session 4: AMS Co-Simulation (Power-Aware / UPF)

We offer a 50% discount to students; please complete this form to avail the discount.

This session explores how UPF power intent, boundary management and power-aware UVM work together to verify low-power mixed-signal designs.

You will cover SystemVerilog, Verilog-AMS and SPICE basics, UPF 1801 fundamentals, power domains and power state tables, threshold mapping, isolation and level shifting, the VCS-NLP compilation flow, power-aware UVM sequencing, mixed-signal power-aware debugging in Verdi, and X-corruption and convergence analysis.

The live demonstrations build a CMOS inverter, run it through analog-to-digital conversion under UPF power intent, create an isolation cell for boundary management, and analyse X-corruption and convergence in a power-aware UVM environment.

This session is part of a 4-session professional training programme:

• Session 1 — Analog IC Design using Python: GM/ID Methodology

• Session 2 — Verilog-AMS, SystemVerilog-AMS & UVM-AMS

• Session 3 — AMS Co-Simulation (RNM & UVM)

• Session 4 — AMS Co-Simulation (Power-Aware / UPF)

REGISTRATION FOR ALL 4 SESSIONS IS 150$ ONLY.

What You Will Learn

• SystemVerilog, Verilog-AMS and SPICE basics

• UPF 1801 fundamentals

• Power domains and power state tables

• Threshold mapping

• Isolation and level shifting

• The VCS-NLP compilation flow

• Power-aware UVM sequencing

• Mixed-signal power-aware debugging in Verdi

• X-corruption and convergence analysis

Why This Matters

Low-power mixed-signal designs must be verified against their intended power states and boundary behavior. Isolation, level shifting, and power-aware sequencing affect signal behavior as power conditions change.

This session demonstrates how UPF power intent can be applied and how engineers can investigate X-corruption and convergence issues in a power-aware verification environment.

Ideal For

• AMS verification engineers

• Low-power design verification engineers

• Analog and mixed-signal design engineers

• Engineers working with UPF and power-aware UVM

Prior exposure to the corresponding full-length course is helpful but not required.

Training Format

• 3-hour live online training session

• Four condensed teaching blocks

• Three live demonstrations

• CMOS inverter simulation under UPF power intent

• Isolation-cell creation for boundary management

• X-corruption and convergence analysis in a power-aware UVM environment

• Short quizzes after each taught block

• Midpoint break and ten-minute closing Q&A

This session is Session 4 of the 4-session Analog and Mixed-Signal Design and Verification — Intensive Track.