[3 sessions] CPU Verification

[3 sessions] CPU Verification

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This is a 3-session professional training programme covering CPU architecture and CPU-level verification, from instruction set architecture (ISA) fundamentals to a running multi-core RISC-V system.

The programme progresses from understanding the RISC-V ISA and a single-cycle CVA6 core to multi-core execution on OpenPiton silicon and CPU-level verification using industry tools.

The programme consists of three sessions:

• Session 1 — Fundamentals of the RISC-V ISA

• Session 2 — From One Core to Many

• Session 3 — Verifying a CPU, Not Just a Block

What You Will Learn

By the end of this programme, you will:

• Understand ISA standardisation, RISC versus CISC and RISC-V instruction formats

• Explore CPU organisation, memory layout, addressing modes and privilege modes

• Understand registers, calling conventions, control and status registers, traps and interrupts

• Explore pipelining, forwarding, stalls and out-of-order issue

• Understand multi-core RISC-V systems, HARTs and shared memory

• Apply golden-model comparison using Spike

• Generate directed and random instruction streams using RISC-V-DV

• Run RISC-V compliance test suites

• Understand CPU-level verification processes, metrics and testbench quality

• Explore directed formal verification and mutation testing

Why This Matters

CPU verification requires more than checking individual RTL blocks. Engineers must understand instruction execution, processor architecture, multi-core behaviour and the evidence needed to sign off a complete CPU.

This programme progresses from ISA fundamentals to real multi-core execution and CPU-level verification against golden models and compliance suites.

Ideal For

• Engineers new to CPU architecture and verification

• Verification engineers moving from block-level to CPU-level verification

• Engineers interested in RISC-V architecture and processor verification

Basic digital-logic familiarity is required. No prior RISC-V or UVM experience is needed.

Training Format

• 3 sessions

• 2 hours per session

• 6 hours in total

• Live online training

• 6 live demonstrations, two per session

• Demonstrations using RARS, CVA6, OpenPiton, Spike, RISC-V-DV and RISC-V compliance suites

• Ten-minute break and five-minute quiz at the midpoint of each session

• Course materials and quiz discussions

Participants need a laptop and a stable internet connection.