CPU Verification | Session 1: Fundamentals of the RISC-V ISA

CPU Verification | Session 1: Fundamentals of the RISC-V ISA

We offer a 50% discount to students; please complete this form to avail the discount.

This session introduces instruction set architecture (ISA) fundamentals and explores how RISC-V puts these concepts into practice.

You will cover ISA standardisation, operand-storage classes, RISC versus CISC, instruction formats, CPU organisation, memory layout, addressing modes, RISC-V extensions and privilege modes.

The live demonstrations measure execution cycles and compare RISC-V assembly programs in RARS, then examine the front-end of a real single-cycle CVA6 core, including fetch, decode, control unit and register file, using UVM and formal verification.

This session is part of a 3-session professional training programme:

• Session 1 — Fundamentals of the RISC-V ISA

• Session 2 — From One Core to Many

• Session 3 — Verifying a CPU, Not Just a Block

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• ISA standardisation and operand-storage classes

• RISC versus CISC

• Instruction formats from three-address to zero-address

• CPU organisation

• Memory layout and addressing modes

• RISC-V base ISA and standard extensions

• The six RISC-V instruction formats

• Privilege modes

Why This Matters

Understanding the ISA provides the foundation for understanding how a processor executes instructions and how its architecture is verified.

This session connects assembly-level behaviour with the actual implementation of a single-cycle CPU.

Ideal For

• Engineers new to CPU architecture

• Verification engineers developing their RISC-V knowledge

• RTL designers interested in processor architecture

• Engineers preparing for CPU-level verification

Basic digital-logic familiarity is required. No prior RISC-V or UVM experience is needed.

Training Format

• 2-hour live online training session

• Concise teaching blocks

• RARS execution-cycle measurement and assembly-program comparison

• CVA6 front-end walkthrough covering fetch, decode, control unit and register file

• UVM and formal verification concepts

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 1 of the 3-session CPU Verification Programme.