CPU Verification | Session 2: From One Core to Many

CPU Verification | Session 2: From One Core to Many

We offer a 50% discount to students; please complete this form to avail the discount.

This session explores how a single-cycle CPU develops into a multi-core RISC-V system.

You will cover registers, calling conventions, control and status registers, traps, interrupts and exceptions, followed by pipelined execution, forwarding, stalls, out-of-order issue, HARTs and shared memory.

The live demonstrations complete the execute, memory and writeback stages of a single-cycle core, then run a factorial program across four and eight real RISC-V HARTs on OpenPiton silicon.

This session is part of a 3-session professional training programme:

• Session 1 — Fundamentals of the RISC-V ISA

• Session 2 — From One Core to Many

• Session 3 — Verifying a CPU, Not Just a Block

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• CPU registers and calling conventions

• Control and status registers

• Traps, interrupts and exceptions

• The transition from single-cycle to pipelined execution

• Forwarding and stalls

• Out-of-order issue

• Multi-core RISC-V systems

• The HART model and shared memory

Why This Matters

Moving from a single CPU core to a multi-core system introduces additional architectural and verification considerations, including shared-memory execution and interactions between HARTs.

This session connects CPU microarchitecture with real multi-core execution on OpenPiton silicon.

Ideal For

• Engineers learning CPU architecture

• Verification engineers moving towards CPU-level verification

• RTL designers interested in pipelined and multi-core processors

• Engineers interested in RISC-V execution and shared memory

Basic digital-logic familiarity is required. No prior RISC-V or UVM experience is needed.

Training Format

• 2-hour live online training session

• Concise teaching blocks

• Completing the execute, memory and writeback stages of a single-cycle core

• Running a factorial program across four and eight real RISC-V HARTs on OpenPiton silicon

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 2 of the 3-session CPU Verification Programme.