CPU Verification | Session 3: Verifying a CPU, Not Just a Block

CPU Verification | Session 3: Verifying a CPU, Not Just a Block

We offer a 50% discount to students; please complete this form to avail the discount.

This session focuses on verifying a complete CPU core rather than an individual RTL block.

You will explore why CPU-level verification differs from block-level verification, verification processes and metrics, golden-model comparison, directed formal verification (DFV) and mutation testing.

The live demonstrations generate directed and random instruction streams using RISC-V-DV and compare the results against a Spike golden model, then run RISC-V compliance test suites and compare VCS and Xcelium execution traces against Spike.

This session is part of a 3-session professional training programme:

• Session 1 — Fundamentals of the RISC-V ISA

• Session 2 — From One Core to Many

• Session 3 — Verifying a CPU, Not Just a Block

REGISTRATION FOR ALL 3 SESSIONS IS 60$ ONLY.

What You Will Learn

• Differences between CPU-level and block-level verification

• CPU verification processes and metrics

• Golden-model comparison

• Directed formal verification (DFV)

• Mutation testing and testbench quality

• Directed and random instruction-stream generation

• RISC-V-DV and Spike-based checking

• RISC-V compliance testing

• Comparing VCS and Xcelium execution traces against Spike

Why This Matters

A CPU must execute instructions correctly across its architecture, not merely pass isolated block-level tests. Golden-model comparison, compliance testing and testbench-quality analysis provide complementary evidence for CPU verification.

This session demonstrates how instruction streams and compliance suites can be used to evaluate CPU behaviour against a reference model.

Ideal For

• CPU verification engineers

• Verification engineers moving from block-level to CPU-level work

• RISC-V verification engineers

• Engineers interested in golden-model comparison and compliance sign-off

Basic digital-logic familiarity is required. No prior RISC-V or UVM experience is needed.

Training Format

• 2-hour live online training session

• Concise teaching blocks

• Directed and random instruction-stream generation using RISC-V-DV

• Comparison against the Spike golden model

• RISC-V compliance test suites

• VCS and Xcelium execution-trace comparison against Spike

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 3 of the 3-session CPU Verification Programme.