[6 sessions] Multicore Programming: Development and Verification

[6 sessions] Multicore Programming: Development and Verification

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This is a six-session professional training programme covering multicore RISC-V development and verification, from memory-model fundamentals and multi-hart verification to cache coherency, SoC integration, virtual memory, hypervisors and application-domain SoCs.

The programme combines hardware and software perspectives throughout, using practical demonstrations on implemented designs and open-source tools. Participants explore how to identify concurrency bugs, verify memory ordering, investigate cache-coherency failures and build confidence in a complete multicore system through testing and formal verification.

The programme consists of six sessions:

• Session 1 — Multi-Hart Verification and RVWMO

• Session 2 — HARTBREAKER and the Confirmed Bugs

• Session 3 — Caches, Coherency and Cache-Aware Software

• Session 4 — SoC Integration and Multicore Software

• Session 5 — Virtual Memory and Hypervisors

• Session 6 — Application-Domain SoCs and Sign-Off

What You Will Learn

By the end of this programme, you will:

• Understand multi-hart execution, shared memory and the RISC-V Weak Memory Ordering (RVWMO) model

• Investigate memory-ordering behaviours using Dartagnan, Z3 and HERD7

• Explore HARTBREAKER fuzzing and formal memory-model checking

• Understand cache hierarchies, MESI coherency and directory-based architectures

• Apply cache-aware software techniques, including cache-line padding and synchronization fences

• Verify SoC interconnects, interrupts, DMA coherency and power-domain interactions

• Develop bare-metal symmetric multiprocessing (SMP) software

• Understand Sv39 virtual memory, TLBs, page faults and hypervisor operation

• Explore application-domain verification for automotive, cloud, AI and heterogeneous SoCs

• Apply formal verification, software testing and sign-off techniques across the system

Why This Matters

Multicore systems introduce verification challenges that conventional pass/fail testing alone cannot address. Correct hardware can exhibit different outcomes across executions, and concurrency bugs may remain hidden even after extensive testing.

This programme develops a practical, tool-driven approach to identify and verify these behaviours, connecting hardware architecture, software synchronization, formal reasoning, and full-stack sign-off.

Ideal For

• Hardware verification engineers

• Software verification engineers

• Multicore RISC-V engineers

• Engineers working with CPU architecture and cache coherency

• Engineers involved in SoC integration and system-level verification

Working knowledge of RISC-V ISA concepts, basic UVM and C programming is required.

Training Format

• 6 sessions

• 3 hours per session

• 18 hours in total

• Live online training

• 18 live demonstrations across the programme

• Three practical demonstrations per session

• Demonstrations using implemented designs and open-source tools

• Ten-minute break and five-minute quiz at the midpoint of every session

• Course materials for all six sessions

• Quiz discussion in every session

Tools and Technologies Covered

HARTBREAKER, Spike, Verilator, Dartagnan, Z3, HERD7, UVM, JasperGold, Chipyard, QEMU/KVM, VCS, Xcelium, OpenSBI, GDB, FreeRTOS, Zephyr and other technologies specified in the programme.

Participants need a laptop and a stable internet connection.