Multicore Programming | Session 1: Multi-Hart Verification and RVWMO

Multicore Programming | Session 1: Multi-Hart Verification and RVWMO

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Why can correct hardware return different results across identical runs, and how do you verify outcomes that are permitted by the memory model?

This session introduces multi-hart execution, shared-memory behaviour and the RISC-V Weak Memory Ordering (RVWMO) model. You will explore store-buffer non-determinism, RVWMO axioms, the 13 Preserved Program Order rules, including CoRR, and the limitations of conventional litmus tests and CPU fuzzers.

The session also introduces determinism anchors based on data flow, control flow and synchronization, showing how they help divide test programs into independently checkable sections.

This session is part of a six-session professional training programme:

• Session 1 — Multi-Hart Verification and RVWMO

• Session 2 — HARTBREAKER and the Confirmed Bugs

• Session 3 — Caches, Coherency and Cache-Aware Software

• Session 4 — SoC Integration and Multicore Software

• Session 5 — Virtual Memory and Hypervisors

• Session 6 — Application-Domain SoCs and Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Harts and shared-memory execution

• Store-buffer non-determinism

• The limitations of conventional pass/fail testing

• RVWMO axioms and memory-ordering rules

• The 13 Preserved Program Order rules, including CoRR

• Limitations of litmus tests and CPU fuzzers

• Determinism anchors based on data flow, control flow and synchronization

• Formal checking of memory-model legality using Dartagnan and Z3

Why This Matters

Concurrent programs can produce different results even when the underlying hardware is functioning correctly. Verification therefore requires distinguishing permitted outcomes from genuine architectural violations.

This session establishes the memory-model concepts and verification techniques needed to reason about concurrent RISC-V execution.

Ideal For

• Hardware verification engineers

• Software verification engineers

• RISC-V CPU engineers

• Engineers working with shared memory and concurrent execution

• Engineers interested in formal memory-model verification

Working knowledge of RISC-V ISA concepts, basic UVM and C programming is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Three live demonstrations:

  • Checking whether the classic store-buffer outcome (a=0, b=0) is legal under RVWMO using Dartagnan and Z3

  • Reviewing the measured results of 1,314 PULP and CHERI litmus tests against five production CPUs

  • Generating an anchored test program whose synchronization anchors divide it into independently checkable sections

• Practical memory-model analysis

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 1 of the six-session Multicore Programming: Development and Verification Programme.