Multicore Programming | Session 2: HARTBREAKER and the Confirmed Bugs

Multicore Programming | Session 2: HARTBREAKER and the Confirmed Bugs

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How can fuzzing combined with formal memory-model checking uncover bugs in production out-of-order CPU cores that conventional litmus tests miss?

This session examines the HARTBREAKER verification pipeline, combining the Spike reference model, Verilator-based RTL execution, timeout detection and memory-consistency-model (MCM) checks.

You will explore five CPU designs under test—Rocket, BOOM v4, Toooba, NaxRiscv and XiangShan—and investigate the root causes and fixes for confirmed bugs B1, N1, N2, T1 and X1.

The session also examines the software contract for memory ordering, including FENCE, AMO acquire/release semantics, LR/SC, CBMC, SPIN and HERD7.

This session is part of a six-session professional training programme:

• Session 1 — Multi-Hart Verification and RVWMO

• Session 2 — HARTBREAKER and the Confirmed Bugs

• Session 3 — Caches, Coherency and Cache-Aware Software

• Session 4 — SoC Integration and Multicore Software

• Session 5 — Virtual Memory and Hypervisors

• Session 6 — Application-Domain SoCs and Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• The HARTBREAKER verification pipeline

• The roles of Spike and Verilator in the verification flow

• Timeout detection and MCM legality checks

• Verification of Rocket, BOOM v4, Toooba, NaxRiscv and XiangShan

• Root-cause analysis of confirmed bugs B1, N1, N2, T1 and X1

• FENCE and AMO acquire/release semantics

• LR/SC operations

• Software verification using CBMC and SPIN

• Memory-model checking using Dartagnan and HERD7

Why This Matters

Fuzzing can generate execution scenarios that conventional tests do not cover. However, identifying an unusual result is not sufficient: engineers must establish whether it violates the memory model and trace the failure to a design defect.

This session demonstrates how fuzzing, formal legality checks and root-cause analysis can work together to identify and investigate real CPU bugs.

Ideal For

• CPU verification engineers

• RISC-V hardware engineers

• Software verification engineers

• Engineers working with out-of-order CPU cores

• Engineers interested in fuzzing and formal verification

Working knowledge of RISC-V ISA concepts, basic UVM and C programming is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Three live demonstrations:

  • Running HARTBREAKER from its Docker artifact against a pre-built BOOM simulator

  • Tracing confirmed bugs from RTL defects to upstream fixes, distinguishing timeout-detected bugs T1 and N2 from MCM-detected bugs B1, N1 and X1

  • Checking FENCE and acquire/release placement against RVWMO using Dartagnan and HERD7

• Practical investigation of CPU verification failures

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 2 of the six-session Multicore Programming: Development and Verification Programme.